| 2002 | A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 2002 | Automatic Model Refinement for Fast Architecture Exploration. | Junyu Peng, Samar Abdi, Daniel Gajski |
| 2002 | Development of ASIC Chip-Set for High-End Network Processing Application-A Case Study. | Sanjeev Patel |
| 2002 | Embedded DRAM (eDRAM) Power-Energy Estimation for System-on-a-Chip (SoC) Applications. | Yong-Ha Park, Jeonghoon Kook, Hoi-Jun Yoo |
| 2002 | A Hardware/Software Reconfigurable Architecture for Adaptive Wireless Image Communication. | Debashis Panigrahi, Clark N. Taylor, Sujit Dey |
| 2002 | Systematic Address and Control Code Transformations for Performance Optimisation of a MPEG-4 Video Decoder. | Martin Palkovic, Miguel Miranda, Kristof Denolf, Peter Vos, Francky Catthoor |
| 2002 | Application of Multi-Domain and Multi-Language Cosimulation to an Optical MEM Switch Design. | Gabriela Nicolescu, S. Martinez, Lobna Kriaa, Wassim Youssef, Sungjoo Yoo, Benot Charlot, Ahmed Amine Jerraya |
| 2002 | Embedded Tutorial: Technological Innovations to Advance Scalability and Interconnects in Bulk and SOI. | Sreedhar Natarajan, Andrew Marshall |
| 2002 | Timing Yield Calculation Using an Impulse-Train Approach. | Srinath R. Naidu |
| 2002 | Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models. | Makoto Nagata, Yoshitaka Murasaka, Youichi Nishimori, Takashi Morie, Atsushi Iwata |
| 2002 | Embedded Tutorial: Modeling Parasitic Coupling Effects in Reliability Verification. | N. S. Nagaraj, Poras T. Balsara, Cyrus D. Cantrell |
| 2002 | A Real Delay Switching Activity Simulator Based on Petri Net Modeling. | Ashok K. Murugavel, N. Ranganathan |
| 2002 | A Power Minimization Technique for Arithmetic Circuits by Cell Selection. | Masanori Muroyama, Tohru Ishihara, Akihiko Hyodo, Hiroto Yasuura |
| 2002 | Verification of an Industrial CC-NUMA Server. | Rajarshi Mukherjee, Yozo Nakayama, Toshiya Mima |
| 2002 | A New Divide and Conquer Method for Achieving High Speed Division in Hardware. | Murali Mohan, Rohini Krishnan, Anshul Kumar, M. Balakrishnan |
| 2002 | Consumer Digitization: Accelerating DSP Applications, Growing VLSI Design Challenges. | Biswadip Mitra |
| 2002 | Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language. | Prabhat Mishra, Hiroyuki Tomiyama, Ashok Halambi, Peter Grun, Nikil D. Dutt, Alexandru Nicolau |
| 2002 | Reducing Library Development Cycle Time through an Optimum Layout Create Flow. | Rituparna Mandal, Dibyendu Goswami, Arup Dash |
| 2002 | Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks. | Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu |
| 2002 | Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded Systems. | Jiong Luo, Niraj K. Jha |
| 2002 | Weight-Based Bus-Invert Coding for Low-Power Applications. | Rung-Bin Lin, Chi-Ming Tsai |
| 2002 | Estimation of Maximum Power-Up Current. | Fei Li, Lei He, Kewal K. Saluja |
| 2002 | Electromigration Avoidance in Analog Circuits: Two Methodologies for Current-Driven Routing. | Jens Lienig, Goeran Jerke, Thorsten Adler |
| 2002 | Mode Selection and Mode-Dependency Modeling for Power-Aware Embedded Systems. | Dexin Li, Pai H. Chou, Nader Bagherzadeh |
| 2002 | ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs. | Haris Lekatsas, Jrg Henkel |