| 2002 | Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon. | Karanth Shankaranarayana, Soujanna Sarkar, R. Venkatraman, Shyam S. Jagini, N. Venkatesh, Jagdish C. Rao, H. Udayakumar, M. Sambandam, K. P. Sheshadri, S. Talapatra, Parag Mhatre, Jais Abraham, Rubin A. Parekhji |
| 2002 | Hardware-Software Co-Synthesis of Low Power Real-Time Distributed Embedded Systems with Dynamically Reconfigurable FPGAs. | Li Shang, Niraj K. Jha |
| 2002 | VLSI Implementation of 2-D DWT/IDWT Cores Using 9/7-Tap Filter Banks Based on the Non-Expansive Symmetric Extension Scheme. | Kavish Seth, S. Srinivasan |
| 2002 | Digital Watermarking. | Martin F. H. Schuurmans |
| 2002 | Architecture Implementation Using the Machine Description Language LISA. | Oliver Schliebusch, Andreas Hoffmann, Achim Nohl, Gunnar Braun, Heinrich Meyr |
| 2002 | Register Transfer Operation Analysis during Data Path Verification. | Dipankar Sarkar |
| 2002 | Synthesis of High Performance Low Power Dynamic CMOS Circuits. | Debasis Samanta, Nishant Sinha, Ajit Pal |
| 2002 | Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits. | Debasis Samanta, Ajit Pal |
| 2002 | An Upper Bound for 3D Slicing Floorplans. | Silke Salewski, Erich Barke |
| 2002 | Design of Asynchronous Controllers with Delay Insensitive Interface. | Hiroshi Saito, Alex Kondratyev, Takashi Nanya |
| 2002 | Improvement of ASIC Design Processes. | Vineet Sahula, C. P. Ravikumar, D. Nagchoudhuri |
| 2002 | Automatic Synthesis of CMOS Operational Amplifiers: A Fuzzy Optimization Approach. | Biranchinath Sahu, Aloke K. Dutta |
| 2002 | A Completely Integrated Low Jitter CMOS PLL for Analog Front Ends in Systems on Chip Environment. | Debapriya Sahu |
| 2002 | Evaluation of Statistical Outlier Rejection Methods for IDDQ Limit Setting. | Sagar S. Sabade, D. M. H. Walker |
| 2002 | Trends and Challenges in VLSI Technology Scaling towards 100nm (Tutorial Abstract). | Stefan Rusu, Manoj Sachdev, Christer Svensson, Bram Nauta |
| 2002 | Degree-of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area. | Samir Roy, Biplab K. Sikdar, Monalisa Mukherjee, Debesh K. Das |
| 2002 | Functional Verification of System on Chips-Practices, Issues and Challenges (Tutorial Abstract). | Subir K. Roy, S. Ramesh, Supratik Chakraborty, Tsuneo Nakata, Sreeranga P. Rajan |
| 2002 | Test Solution for OTA Based Analog Circuits. | Baidya Nath Ray, Parimal Pal Chaudhuri, Prasanta Kumar Nandi |
| 2002 | Divide-and-Conquer IDDQ Testing for Core-Based System Chips. | C. P. Ravikumar, Rahul Kumar |
| 2002 | Low Power Solution for Wireless Applications. | Sornavalli Ramanathan, Rituparna Mandal |
| 2002 | Address Code and Arithmetic Optimizations for Embedded Systems. | J. Ramanujam, Satish Krishnamurthy, Jinpyo Hong, Mahmut T. Kandemir |
| 2002 | A Heuristic for Clock Selection in High-Level Synthesis. | J. Ramanujam, Sandeep Deshpande, Jinpyo Hong, Mahmut T. Kandemir |
| 2002 | A New Synthesis of Symmetric Functions. | Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya |
| 2002 | High-Level Synthesis with SIMD Units. | Vijay Raghunathan, Anand Raghunathan, Mani B. Srivastava, Milos D. Ercegovac |
| 2002 | Identifying Redundant Wire Replacements for Synthesis and Verification. | Katarzyna Radecka, Zeljko Zilic |