| 2014 | Layout-Aware Delay Variation Optimization for CNTFET-Based Circuits. | Matthias Beste, Saman Kiamehr, Mehdi Baradaran Tahoori |
| 2014 | Temperature Minimization Using Power Redistribution in Embedded Systems. | Rehan Ahmed, Parameswaran Ramanathan, Kewal K. Saluja |
| 2014 | Process-Variation Aware Multi-temperature Test Scheduling. | Nima Aghaee, Zebo Peng, Petru Eles |
| 2013 | Energy-efficient and Secure Sensor Data Transmission Using Encompression. | Meng Zhang, Mehran Mozaffari Kermani, Anand Raghunathan, Niraj K. Jha |
| 2013 | Fin Prin: Analysis and Optimization of FinFET Logic Circuits under PVT Variations. | Yang Yang, Niraj K. Jha |
| 2013 | Reducing Test Time of Power Constrained Test by Optimal Selection of Supply Voltage. | Praveen Venkataramani, Vishwani D. Agrawal |
| 2013 | Multiphase Technique to Speed-up Delay Measurement via Sub-sampling. | Rajath Vasudevamurthy, Bharadwaj Amrutur |
| 2013 | Accelerating 3D-FFT Using Hard Embedded Blocks in FPGAs. | B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan |
| 2013 | A High Throughput Multiplier Design Exploiting Input Based Statistical Distribution in Completion Delays. | Ravi Tej Uppu, Ravi Kanth Uppu, Adit D. Singh, Abhijit Chatterjee |
| 2013 | MAPro: A Tiny Processor for Reconfigurable Baseband Modulation Mapping. | Liang Tang, Jude Angelo Ambrose, Sri Parameswaran |
| 2013 | A Fully Integrated CMOS Class-E Power Amplifier for Reconfigurable Transmitters with WCDMA/WiMAX Applications. | Hyuksu Son, Woo Young Kim, Joo Young Jang, Hae Jin Lee, Inn Yeal Oh, Chul Soon Park |
| 2013 | A 50nW, 100kbps Clock/Data Recovery Circuit in an FSK RF Receiver on a Body Sensor Node. | Aatmesh Shrivastava, Jagdish Nayayan Pandey, Brian P. Otis, Benton H. Calhoun |
| 2013 | Design and Implementation of a High Speed MAP Decoder Architecture for Turbo Decoding. | Rahul Shrestha, Roy P. Paily |
| 2013 | Optimum Test Schedule for SoC with Specified Clock Frequencies and Supply Voltages. | Vijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal |
| 2013 | Design of a Fault Tolerant Reversible Compact Unidirectional Barrel Shifter. | Md. Shamsujjoha, Hafiz Md. Hasan Babu, Lafifa Jamal, Ahsan Raja Chowdhury |
| 2013 | A Low Power Fault Tolerant Reversible Decoder Using MOS Transistors. | Md. Shamsujjoha, Hafiz Md. Hasan Babu |
| 2013 | Keynote talk: Deciphering the brain, cousin to the chip. | Lou Scheffer |
| 2013 | Memory Efficient Implementation of Two Graph Based Circuit Simulator for PDE-Electrical Analogy. | Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar |
| 2013 | Geometry Independent Wirelength Estimation Method in VLSI Routing. | Raka Sardar, Ratna Mondal, Tuhina Samanta |
| 2013 | A 40nm 650Mhz 0.5fJ/Bit/Search TCAM Compiler Using Complementary Bit-cell Architecture. | Rashmi Sachan, Shahid Ali, Chandan Bist, Sunil Misra, Vinod Menezes, Sharad Gupta, Pat Bosshart |
| 2013 | Prediction Schemes for Compensating Variable Delay for Improving Performance of Real-Time Control Tasks. | Saptarshi Roy, Amit Patra, Partha Pratim Chakrabarti, Purnendu Sinha, Dipankar Das |
| 2013 | Embedded tutorial - Can silicon machines match the efficiency of the human brain? | Bipin Rajendran |
| 2013 | Efficient Signal Selection Using Fine-grained Combination of Scan and Trace Buffers. | Kamran Rahmani, Prabhat Mishra |
| 2013 | A Study on Instruction-set Selection Using Multi-application Based Application Specific Instruction-set Processors. | Roshan G. Ragel, Swarnalatha Radhakrishnan, Jude Angelo Ambrose, Sri Parameswaran |
| 2013 | Embedded tutorial - Emerging memory technologies: What it means for computer system designers. | Moinuddin K. Qureshi |