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International Conference on VLSI Design

VLSID

National

CORE rank

CORE rank (raw)

National: India

Fields of research

Distributed Computing and Systems Software

Papers indexed

3,530

1992–2026

Papers per year

1992175 peak2026

VLSID papers

3,530 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2003Exploiting Ghost-FSMs as a BIST Structure for Sequential Machines.Samir Roy, Ujjwal Maulik, Biplab K. Sikdar
2003A New Reactive Processor with Architectural Support for Control Dominated Embedded Systems.Partha S. Roop, Zoran A. Salcic, Morteza Biglari-Abhari, Abbas Bigdeli
2003Synthesis Of Programmable Current Mode Linear Analog Circuit.Baidya Nath Ray, Parimal Pal Chaudhuri, Prasanta Kumar Nandi, P. K. Ghosh
2003Efficient RTL Power Estimation for Large Designs.Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar
2003Embedding Security in Wireless Embedded Systems.Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar
2003Mutual Testing based on Wavelet Transforms.C. P. Ravikumar, Nitin Kakkar, Saurabh Chopra
2003New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss.Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal
2003System Support for Embedded Applications.Krithi Ramamritham, Kavi Arya
2003Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program.Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
2003A Run-Time Reconfigurable System for Gene-Sequence Searching.Kiran Puttegowda, William Worek, Nicholas Pappas, Anusha Dandapani, Peter Athanas, Allan Dickerman
2003Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy.Vani Prasad, Madhav P. Desai
2003Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Non-Scan Sequential Test Sequences.Irith Pomeranz, Sudhakar M. Reddy
2003A New Approach to Analyze a Sub-micron CMOS Inverter.Manisha Pattanaik, Swapna Banerjee
2003An Efficient Practical Heuristic For Good Ratio-Cut Partitioning.Sachin B. Patkar, H. Narayanan
2003Testing Embedded Cores and SOCs-DFT, ATPG and BIST Solutions.Rubin A. Parekhji
2003Low Power Technology Mapping for LUT based FPGA "A Genetic Algorithm Approach".Rohit Pandey, Santanu Chattopadhyay
2003CMOS Digital Imager Design from a System-on-a-chip Perspective.Bedabrata Pain, Bruce Hancock, Thomas Cunningham, Guang Yang, Suresh Seshadri, Julie Heynssens, Chris Wrigley
2003Transition Activity Estimation for General Correlated Data Distributions.Alberto Garca Ortiz, Tudor Murgan, Manfred Glesner
2003Narrow Band Noise Suppression Scheme for improving Signal to Noise Ratio.Anantha Nag, K. Radhakrishna Rao
2003Comparison of Heuristic Algorithms for Variable Partitioning in Circuit Implementation.Muthukumar Venkatesan, Henry Selvaraj
2003A Game-Theoretic Approach for Binding in Behavioral Synthesis.Ashok K. Murugavel, N. Ranganathan
2003Design of a high speed string matching co-processor for NLP.Vadali Srinivasa Murty, P. C. Reghu Raj, S. Raman
2003A Novel Architecture for Lifting-Based Discrete Wavelet Transform for JPEG2000 Standard suitable for VLSI.Srikar Movva, S. Srinivasan
2003Detailed Analysis of FIBL in MOS Transistors with High-K Gate Dielectrics.Nihar R. Mohapatra, Madhav P. Desai, V. Ramgopal Rao
2003A Framework for Energy and Transient Power Reduction during Behavioral Synthesis.Saraju P. Mohanty, N. Ranganathan
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