| 2026 | ACL | ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning. | Zhirong Chen, Kaiyan Chang, Zhuolin Li, Cangyuan Li, Xinyang He, Chujie Chen, Mengdi Wang, Haobo Xu, Yinhe Han, Huawei Li, Ying Wang |
| 2026 | ASPDAC | AssertMiner: Module-Level Spec Generation and Assertion Mining using Static Analysis Guided LLMs. | Hongqin Lyu, Yonghao Wang, Jiaxin Zhou, Zhiteng Chao, Tiancheng Wang, Huawei Li |
| 2026 | DATE | Think with Self-Decoupling and Self-Verification: Automated RTL Design with Backtrack-ToT. | Zhiteng Chao, Yonghao Wang, Xinyu Zhang, Jiaxin Zhou, Tenghui Hua, Husheng Han, Tianmeng Yang, Jianan Mu, Bei Yu, Rui Zhang, Jing Ye, Huawei Li |
| 2026 | DATE | ReBIT: A ReRAM-Based In-Situ Training Accelerator with Robustness Against Stochasticity. | Peng Dang, Wei Wang, Yintao He, Huawei Li |
| 2026 | DATE | RAPID: Accelerating Point Cloud Diffusion Models via Space-Aware Mix-Precision Quantization. | Qichu Sun, Yanan Zhu, Linxi Lu, Haishuang Fan, Jingya Wu, Huawei Li, Xiaowei Li, Guihai Yan |
| 2026 | DATE | CoverAssert: Iterative LLM Assertion Generation Driven by Functional Coverage via Syntax-Semantic Representations. | Yonghao Wang, Yang Yin, Hongqin Lyu, Jiaxin Zhou, Zhiteng Chao, Mingyu Shi, Wenchao Ding, Yunlin Du, Jing Ye, Tiancheng Wang, Huawei Li |
| 2026 | DATE | From Buffers to Registers: Unlocking Fine-Grained FlashAttention with Hybrid-Bonded 3D NPU Co-Design. | Jinxin Yu, Yudong Pan, Mengdi Wang, Huawei Li, Yinhe Han, Xiaowei Li, Ying Wang |
| 2026 | ETS | Iterative LLM-Based Assertion Generation Using Syntax-Semantic Representations for Functional Coverage-Guided Verification. | Yonghao Wang, Jiaxin Zhou, Yang Yin, Hongqin Lyu, Zhiteng Chao, Wenchao Ding, Jing Ye, Tiancheng Wang, Huawei Li |
| 2025 | ASPDAC | ETPG: Efficient Transition Fault Simulation via Dual-Strategy Pattern Parallelism and Gate Restructuring. | Mingjun Wang, Hui Wang, Zizhen Liu, Feng Gu, Jianan Mu, Jiaping Tang, Jun Gao, Huawei Li, Jing Ye, Xiaowei Li |
| 2025 | ASPLOS | PAPI: Exploiting Dynamic Parallelism in Large Language Model Decoding with a Processing-In-Memory-Enabled Computing System. | Yintao He, Haiyu Mao, Christina Giannoula, Mohammad Sadrosadati, Juan Gmez-Luna, Huawei Li, Xiaowei Li, Ying Wang, Onur Mutlu |
| 2025 | DAC | PastATPG: A Hybrid ATPG Framework for Better Test Compaction with Partial Assignment SAT. | Zhiteng Chao, Xindi Zhang, Xinyu Zhang, Jianan Mu, Zizhen Liu, Shengwen Liang, Shaowei Cai, Jing Ye, Xiaowei Li, Huawei Li |
| 2025 | DAC | MOSS: Multi-Modal Representation Learning on Sequential Circuits. | Mingjun Wang, Bin Sun, Jianan Mu, Feng Gu, Boyu Han, Tianmeng Yang, Xinyu Zhang, Silin Liu, Yihan Wen, Hui Wang, Jun Gao, Zhiteng Chao, Husheng Han, Zizhen Liu, Shengwen Liang, Jing Ye, Bei Yu, Xiaowei Li, Huawei Li |
| 2025 | DAC | EPICS: Efficient Parallel Pattern Fault Simulation for Sequential Circuits via Strongly Connected Components. | Mingjun Wang, Hui Wang, Jianan Mu, Xinyu Zhang, Bin Sun, Yihan Wen, Zizhen Liu, Feng Gu, Jun Gao, Shengwen Liang, Jing Ye, Xiaowei Li, Huawei Li |
| 2025 | DATE | An Efficient Parallel Fault Simulator for Functional Patterns on Multi-Core Systems. | Xiaoze Lin, Liyang Lai, Huawei Li, Biwei Xie, Xingquan Li |
| 2025 | DATE | ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy. | Jiaping Tang, Jianan Mu, Silin Liu, Zizhen Liu, Feng Gu, Xinyu Zhang, Leyan Wang, Shengwen Liang, Jing Ye, Huawei Li, Xiaowei Li |
| 2025 | HPCA | NeuVSA: A Unified and Efficient Accelerator for Neural Vector Search. | Ziming Yuan, Lei Dai, Wen Li, Jie Zhang, Shengwen Liang, Ying Wang, Cheng Liu, Huawei Li, Xiaowei Li, Jiafeng Guo, Peng Wang, Renhai Chen, Gong Zhang |
| 2025 | ICCAD | RTPU: Unifying Non-Private and Private Inference with Reconfigurable Architecture. | Fuping Li, Ying Wang, Yinghao Yang, Jingxuan Li, Yibo Du, Huawei Li, Yinhe Han, Hang Lu, Xiaowei Li |
| 2025 | ICCAD | VIRTUAL: Vector-based Dynamic Power Estimation via Decoupled Multi-Modality Learning. | Yuntao Lu, Mingjun Wang, Yihan Wen, Boyu Han, Jianan Mu, Huawei Li, Bei Yu |
| 2025 | ICCAD | RIROS: A Parallel RTL Fault SImulation FRamework with TwO-Dimensional Parallelism and Unified Schedule. | Jiaping Tang, Jianan Mu, Zizhen Liu, Ge Yu, Tenghui Hua, Bin Sun, Silin Liu, Jing Ye, Huawei Li |
| 2025 | ICDE | FrontOrder: Frontier-Guided Graph Reordering. | Xinmiao Zhang, Cheng Liu, Shengwen Liang, Chenwei Xiong, Yu Zhang, Lei Zhang, Huawei Li, Xiaowei Li |
| 2025 | ICML | Bridging Layout and RTL: Knowledge Distillation based Timing Prediction. | Mingjun Wang, Yihan Wen, Bin Sun, Jianan Mu, Juan Li, Xiaoyi Wang, Jing Justin Ye, Bei Yu, Huawei Li |
| 2025 | ISCAS | A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs. | Peng Dang, Huawei Li, Wei Wang |
| 2025 | ICSE | Datalog-Based Language-Agnostic Change Impact Analysis for Microservices. | Qingkai Shi, Xiaoheng Xie, Xianjin Fu, Peng Di, Huawei Li, Ang Zhou, Gang Fan |
| 2025 | ITC | TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration. | Zhiteng Chao, Rengang Zhang, Feng Gu, Hongqin Lyu, Bin Sun, Wenxing Li, Zizhen Liu, Jianan Mu, Jing Ye, Xiaowei Li, Huawei Li |
| 2025 | MICRO | LLMulator: Generalizable Cost Modeling for Dataflow Accelerators with Input-Adaptive Control Flow. | Kaiyan Chang, Wenlong Zhu, Shengwen Liang, Huawei Li, Ying Wang |
| 2025 | PPoPP | Frontier-guided Graph Reordering. | Xinmiao Zhang, Cheng Liu, Shengwen Liang, Chenwei Xiong, Yu Zhang, Lei Zhang, Huawei Li, Xiaowei Li |
| 2025 | SC | DRIM-ANN: An Approximate Nearest Neighbor Search Engine based on Commercial DRAM-PIMs. | Mingkai Chen, Tianhua Han, Cheng Liu, Shengwen Liang, Kuai Yu, Lei Dai, Ziming Yuan, Ying Wang, Lei Zhang, Huawei Li, Xiaowei Li |
| 2025 | VTS | HighTPI: A Hierarchical Graph Based Intelligent Method for Test Point Insertion. | Zhiteng Chao, Bin Sun, Hongqin Lyu, Ge Yu, Minjun Wang, Wenxing Li, Zizhen Liu, Jianan Mu, Shengwen Liang, Jing Ye, Xiaowei Li, Huawei Li |
| 2024 | ASPDAC | A Fast Test Compaction Method for Commercial DFT Flow Using Dedicated Pure-MaxSAT Solver. | Zhiteng Chao, Xindi Zhang, Junying Huang, Jing Ye, Shaowei Cai, Huawei Li, Xiaowei Li |
| 2024 | ASPDAC | APoX: Accelerate Graph-Based Deep Point Cloud Analysis via Adaptive Graph Construction. | Lei Dai, Shengwen Liang, Ying Wang, Huawei Li, Xiaowei Li |
| 2024 | ASPDAC | iEDA: An Open-source infrastructure of EDA. | Xingquan Li, Zengrong Huang, Simin Tao, Zhipeng Huang, Chunan Zhuang, Hao Wang, Yifan Li, Yihang Qiu, Guojie Luo, Huawei Li, Haihua Shen, Mingyu Chen, Dongbo Bu, Wenxing Zhu, Ye Cai, Xiaoming Xiong, Ying Jiang, Yi Heng, Peng Zhang, Bei Yu, Biwei Xie, Yungang Bao |
| 2024 | ASPDAC | Chipletizer: Repartitioning SoCs for Cost-Effective Chiplet Integration. | Fuping Li, Ying Wang, Yujie Wang, Mengdi Wang, Yinhe Han, Huawei Li, Xiaowei Li |
| 2024 | DAC | Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework. | Kaiyan Chang, Kun Wang, Nan Yang, Ying Wang, Dantong Jin, Wenlong Zhu, Zhirong Chen, Cangyuan Li, Hao Yan, Yunhao Zhou, Zhuoliang Zhao, Yuan Cheng, Yudong Pan, Yiqi Liu, Mengdi Wang, Shengwen Liang, Yinhe Han, Huawei Li, Xiaowei Li |
| 2024 | DAC | Chiplever: Towards Effortless Extension of Chiplet-based System for FHE. | Yibo Du, Ying Wang, Bing Li, Fuping Li, Shengwen Liang, Huawei Li, Xiaowei Li, Yinhe Han |
| 2024 | DAC | SmartATPG: Learning-based Automatic Test Pattern Generation with Graph Convolutional Network and Reinforcement Learning. | Wenxing Li, Hongqin Lyu, Shengwen Liang, Tiancheng Wang, Huawei Li |
| 2024 | DAC | Drift: Leveraging Distribution-based Dynamic Precision Quantization for Efficient Deep Neural Network Acceleration. | Lian Liu, Zhaohui Xu, Yintao He, Ying Wang, Huawei Li, Xiaowei Li, Yinhe Han |
| 2024 | DAC | Alchemist: A Unified Accelerator Architecture for Cross-Scheme Fully Homomorphic Encryption. | Jianan Mu, Husheng Han, Shangyi Shi, Jing Ye, Zizhen Liu, Shengwen Liang, Meng Li, Mingzhe Zhang, Song Bian, Xing Hu, Huawei Li, Xiaowei Li |
| 2024 | DATE | GPACE: An Energy-Efficient PQ-Based GCN Accelerator with Redundancy Reduction. | Yibo Du, Shengwen Liang, Ying Wang, Huawei Li, Xiaowei Li, Yinhe Han |
| 2024 | DATE | Bit-Trimmer: Ineffectual Bit-Operation Removal for CLM Architecture. | Yintao He, Shixin Zhao, Songyun Qu, Huawei Li, Xiaowei Li, Ying Wang |
| 2024 | DATE | HyQA: Hybrid Near-Data Processing Platform for Embedding Based Question Answering System. | Shengwen Liang, Ziming Yuan, Ying Wang, Dawen Xu, Huawei Li, Xiaowei Li |
| 2024 | ETS | A Fully Pipelined High-Performance Elliptic Curve Cryptography Processor for NIST P-256. | Han Yan, Shuai Chen, Junying Huang, Jing Ye, Huawei Li, Xiaowei Li |
| 2024 | EuroPar | Athena: Add More Intelligence to RMT-Based Network Data Plane with Low-Bit Quantization. | Yunkun Liao, Hanyue Lin, Jingya Wu, Wenyan Lu, Huawei Li, Xiaowei Li, Guihai Yan |
| 2024 | ICCAD | Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation. | Kaiyan Chang, Zhirong Chen, Yunhao Zhou, Wenlong Zhu, Kun Wang, Haobo Xu, Cangyuan Li, Mengdi Wang, Shengwen Liang, Huawei Li, Yinhe Han, Ying Wang |
| 2024 | ICCAD | AGC: A Unified Architecture for Accelerating K-Nearest Neighbor Graph Construction in Vector Search. | Lei Dai, Ziming Yuan, Wen Li, Shengwen Liang, Kaiwei Zou, Ying Wang, Cheng Liu, Huawei Li, Xiaowei Li |
| 2024 | ICCAD | DDP-Fsim: Efficient and Scalable Fault Simulation for Deterministic Patterns with Two-Dimensional Parallelism. | Feng Gu, Mingjun Wang, Jianan Mu, Zizhen Liu, Jiaping Tang, Hui Wang, Yonghao Wang, Jing Ye, Huawei Li, Xiaowei Li |
| 2024 | ICCAD | HLSPilot: LLM-based High-Level Synthesis. | Chenwei Xiong, Cheng Liu, Huawei Li, Xiaowei Li |
| 2023 | DAC | APPEND: Rethinking ASIP Synthesis in the Era of AI. | Cangyuan Li, Ying Wang, Huawei Li, Yinhe Han |
| 2023 | DATE | Energy-efficient NTT Design with One-bank SRAM and 2-D PE Array. | Jianan Mu, Huajie Tan, Jiawen Wu, Haotian Lu, Chip-Hong Chang, Shuai Chen, Shengwen Liang, Jing Ye, Huawei Li, Xiaowei Li |
| 2023 | DATE | Rethinking NPN Classification from Face and Point Characteristics of Boolean Functions. | Jiaxi Zhang, Shenggen Zheng, Liwei Ni, Huawei Li, Guojie Luo |
| 2023 | ETS | Online Reliability Evaluation Design: Select Reliable CRPs for Arbiter PUF and Its Variants. | Chaofang Ma, Jianan Mu, Jing Ye, Shuai Chen, Yuan Cao, Huawei Li, Xiaowei Li |
| 2023 | ICCAD | DeepBurning-MixQ: An Open Source Mixed-Precision Neural Network Accelerator Design Framework for FPGAs. | Erjing Luo, Haitong Huang, Cheng Liu, Guoyu Li, Bing Yang, Ying Wang, Huawei Li, Xiaowei Li |
| 2023 | ICCAD | Fast Exact NPN Classification with Influence-Aided Canonical Form. | Yonghe Zhang, Liwei Ni, Jiaxi Zhang, Guojie Luo, Huawei Li, Shenggen Zheng |
| 2023 | ICCD | PANG: A Pattern-Aware GCN Accelerator for Universal Graphs. | Yibo Du, Ying Wang, Shengwen Liang, Huawei Li, Xiaowei Li, Yinhe Han |
| 2023 | ICCD | Adaptive Reconvergence-driven AIG Rewriting via Strategy Learning. | Liwei Ni, Zonglin Yang, Jiaxi Zhang, Junfeng Liu, Huawei Li, Biwei Xie, Xinquan Li |
| 2023 | ICCV | Gram-based Attentive Neural Ordinary Differential Equations Network for Video Nystagmography Classification. | Xihe Qiu, Shaojie Shi, Xiaoyu Tan, Chao Qu, Zhijun Fang, Hailing Wang, Yongbin Gao, Peixia Wu, Huawei Li |
| 2023 | ICPADS | Communication-aware Quantization for Deep Learning Inference Parallelization on Chiplet-based Accelerators. | Kaiwei Zou, Songyun Qu, Wen Li, Ying Wang, Huawei Li, Yongpan Liu |
| 2023 | ISCAS | BGNN-HT: Bidirectional Graph Neural Network for Hardware Trojan Cells Detection at Gate Level. | Peiheng Zhan, Haihua Shen, Shan Li, Huawei Li |
| 2022 | ASPDAC | A Voltage Template Attack on the Modular Polynomial Subtraction in Kyber. | Jianan Mu, Yixuan Zhao, Zongyue Wang, Jing Ye, Junfeng Fan, Shuai Chen, Huawei Li, Xiaowei Li, Yuan Cao |
| 2022 | DAC | InfoX: an energy-efficient ReRAM accelerator design with information-lossless low-bit ADCs. | Yintao He, Songyun Qu, Ying Wang, Bing Li, Huawei Li, Xiaowei Li |
| 2022 | DAC | VStore: in-storage graph based vector search accelerator. | Shengwen Liang, Ying Wang, Ziming Yuan, Cheng Liu, Huawei Li, Xiaowei Li |
| 2022 | DATE | NoCeption: A Fast PPA Prediction Framework for Network-on-Chips Using Graph Neural Network. | Fuping Li, Ying Wang, Cheng Liu, Huawei Li, Xiaowei Li |
| 2022 | ICCAD | GIA: A Reusable General Interposer Architecture for Agile Chiplet Integration. | Fuping Li, Ying Wang, Yuanqing Cheng, Yujie Wang, Yinhe Han, Huawei Li, Xiaowei Li |
| 2022 | ICCD | Reexamining CGRA Memory Sub-system for Higher Memory Utilization and Performance. | Lei Dai, Ying Wang, Cheng Liu, Fuping Li, Huawei Li, Xiaowei Li |
| 2022 | UAI | SASH: Efficient secure aggregation based on SHPRG for federated learning. | Zizhen Liu, Si Chen, Jing Ye, Junfeng Fan, Huawei Li, Xiaowei Li |
| 2022 | VTS | Special Session: Fault-Tolerant Deep Learning: A Hierarchical Perspective. | Cheng Liu, Zhen Gao, Siting Liu, Xuefei Ning, Huawei Li, Xiaowei Li |
| 2021 | DAC | GCiM: A Near-Data Processing Accelerator for Graph Construction. | Lei He, Cheng Liu, Ying Wang, Shengwen Liang, Huawei Li, Xiaowei Li |
| 2021 | DAC | TARe: Task-Adaptive in-situ ReRAM Computing for Graph Learning. | Yintao He, Ying Wang, Cheng Liu, Huawei Li, Xiaowei Li |
| 2021 | DAC | PixelSieve: Towards Efficient Activity Analysis From Compressed Video Streams. | Yongchen Wang, Ying Wang, Huawei Li, Xiaowei Li |
| 2021 | VTS | Special Session - Test for AI Chips: from DFT to On-line Testing. | Huawei Li, Xiaowei Li, Yu Huang, Ying Wang, Gary Guo |
| 2021 | USENIX | GLIST: Towards In-Storage Graph Learning. | Cangyuan Li, Ying Wang, Cheng Liu, Shengwen Liang, Huawei Li, Xiaowei Li |
| 2020 | DAC | Towards State-Aware Computation in ReRAM Neural Networks. | Yintao He, Ying Wang, Xiandong Zhao, Huawei Li, Xiaowei Li |
| 2020 | DAC | An Efficient Deep Learning Accelerator for Compressed Video Analysis. | Yongchen Wang, Ying Wang, Huawei Li, Yinhe Han, Xiaowei Li |
| 2020 | DATE | CNT-Cache: an Energy-Efficient Carbon Nanotube Cache with Adaptive Encoding. | Dawen Xu, Kexin Chu, Cheng Liu, Ying Wang, Lei Zhang, Huawei Li |
| 2020 | DATE | HIT: A Hidden Instruction Trojan Model for Processors. | Jiaqi Zhang, Ying Zhang, Huawei Li, Jianhui Jiang |
| 2020 | ICCAD | DeepBurning-GL: an Automated Framework for Generating Graph Neural Network Accelerators. | Shengwen Liang, Cheng Liu, Ying Wang, Huawei Li, Xiaowei Li |
| 2020 | ICCAD | A Many-Core Accelerator Design for On-Chip Deep Reinforcement Learning. | Ying Wang, Mengdi Wang, Bing Li, Huawei Li, Xiaowei Li |
| 2020 | VTS | Special Session - Emerging Memristor Based Memory and CIM Architecture: Test, Repair and Yield Analysis. | Rajendra Bishnoi, Lizhou Wu, Moritz Fieback, Christopher Mnch, Sarath Mohanachandran Nair, Mehdi Baradaran Tahoori, Ying Wang, Huawei Li, Said Hamdioui |
| 2020 | VTS | Sequence Triggered Hardware Trojan in Neural Network Accelerator. | Zizhen Liu, Jing Ye, Xing Hu, Huawei Li, Xiaowei Li, Yu Hu |
| 2020 | VTS | A New Secure Scan Design with PUF-based Key for Authentication. | Qidong Wang, Aijiao Cui, Gang Qu, Huawei Li |
| 2019 | ASPDAC | P | Wen Li, Ying Wang, Huawei Li, Xiaowei Li |
| 2019 | ASPDAC | Exploring emerging CNFET for efficient last level cache design. | Dawen Xu, Li Li, Ying Wang, Cheng Liu, Huawei Li |
| 2019 | DAC | A None-Sparse Inference Accelerator that Distills and Reuses the Computation Redundancy in CNNs. | Ying Wang, Shengwen Liang, Huawei Li, Xiaowei Li |
| 2019 | DAC | Systolic Cube: A Spatial 3D CNN Accelerator Architecture for Low Power Video Analysis. | Yongchen Wang, Ying Wang, Huawei Li, Cong Shi, Xiaowei Li |
| 2019 | DATE | Learn-to-Scale: Parallelizing Deep Learning Inference on Chip Multiprocessor Architecture. | Kaiwei Zou, Ying Wang, Huawei Li, Xiaowei Li |
| 2019 | FPL | InS-DLA: An In-SSD Deep Learning Accelerator for Near-Data Processing. | Shengwen Liang, Ying Wang, Cheng Liu, Huawei Li, Xiaowei Li |
| 2019 | ICCAD | An Agile Precision-Tunable CNN Accelerator based on ReRAM. | Yintao He, Ying Wang, Yongchen Wang, Huawei Li, Xiaowei Li |
| 2019 | ICCD | RRAMedy: Protecting ReRAM-Based Neural Network from Permanent and Soft Faults During Its Lifetime. | Wen Li, Ying Wang, Huawei Li, Xiaowei Li |
| 2019 | ICNC | Resource Bottleneck Analysis of the Blockchain Based on Tron's TPS. | Huawei Li, Zhihuai Li, Na Tian |
| 2019 | IOLTS | iATPG: Instruction-level Automatic Test Program Generation for Vulnerabilities under DVFS attack. | Kuozhong Zhang, Junying Huang, Jing Ye, Xiaochun Ye, Da Wang, Dongrui Fan, Huawei Li, Xiaowei Li, Zhimin Zhang |
| 2019 | ITC | International Test Conference in Asia (ITC-Asia) - Bridging ITC and Test Community in Asia. | Kuen-Jong Lee, Shi-Yu Huang, Huawei Li, Tomoo Inoue, Yervant Zorian |
| 2019 | ITC | China Test Conference (CTC) - Extending the Global Test Forum to China. | Huawei Li, Xiaowei Li, Yinhe Han |
| 2019 | VTS | A Secure and Low-overhead Active IC Metering Scheme. | Aijiao Cui, Yan Yang, Gang Qu, Huawei Li |
| 2019 | VTS | Leveraging Memory PUFs and PIM-based encryption to secure edge deep learning systems. | Wen Li, Ying Wang, Huawei Li, Xiaowei Li |
| 2019 | USENIX | Cognitive SSD: A Deep Learning Engine for In-Storage Data Retrieval. | Shengwen Liang, Ying Wang, Youyou Lu, Zhe Yang, Huawei Li, Xiaowei Li |
| 2018 | ASPDAC | A low-overhead PUF based on parallel scan design. | Wenxuan Wang, Aijiao Cui, Gang Qu, Huawei Li |
| 2018 | ASPDAC | XORiM: A case of in-memory bit-comparator implementation and its performance implications. | Kaiwei Zou, Ying Wang, Huawei Li, Xiaowei Li |
| 2018 | DATE | A retrospective evaluation of energy-efficient object detection solutions on embedded devices. | Ying Wang, Zhenyu Quan, Jiajun Li, Yinhe Han, Huawei Li, Xiaowei Li |
| 2018 | ICCAD | FCN-engine: accelerating deconvolutional layers in classic CNN processors. | Dawen Xu, Kaijie Tu, Ying Wang, Cheng Liu, Bingsheng He, Huawei Li |
| 2018 | ITC | Lightweight Timing Channel Protection for Shared DRAM Controller. | Ying Wang, Wen Li, Huawei Li, Xiaowei Li |
| 2018 | VTS | Innovative practices on challenges, opportunities, and solutions to hardware security. | Sohrab Aftabjahani, Jason Oberg, Michael Chen, Huawei Li |
| 2018 | VTS | Modeling attacks on strong physical unclonable functions strengthened by random number and weak PUF. | Jing Ye, Qingli Guo, Yu Hu, Huawei Li, Xiaowei Li |
| 2017 | ASPDAC | ApproxPIM: Exploiting realistic 3D-stacked DRAM for energy-efficient processing in-memory. | Yibin Tang, Ying Wang, Huawei Li, Xiaowei Li |
| 2017 | DAC | Real-Time Meets Approximate Computing: An Elastic CNN Inference Accelerator with Adaptive Trade-off between QoS and QoR. | Ying Wang, Huawei Li, Xiaowei Li |
| 2017 | IROS | A regularized on-line sequential extreme learning machine with forgetting property for fast dynamic hysteresis modeling. | Zelong Wu, Hui Tang, Sifeng He, Jian Gao, Xin Chen, Chengqiang Cui, Yunbo He, Kai Zhang, Huawei Li, Yangmin Li |
| 2017 | ITC | Software-based online self-testing of network-on-chip using bounded model checking. | Ying Zhang, Krishnendu Chakrabarty, Huawei Li, Jianhui Jiang |
| 2017 | VTS | Flip-flop clustering based trace signal selection for post-silicon debug. | Yun Cheng, Huawei Li, Ying Wang, Yingke Gao, Bo Liu, Xiaowei Li |
| 2017 | VTS | Innovative practices session 10C formal verification practices in industry. | Huawei Li, Xiaowei Li |
| 2016 | DAC | DISCO: a low overhead in-network data compressor for energy-efficient chip multi-processors. | Ying Wang, Yinhe Han, Jun Zhou, Huawei Li, Xiaowei Li |
| 2016 | DAC | DeepBurning: automatic generation of FPGA-based learning accelerators for the neural network family. | Ying Wang, Jie Xu, Yinhe Han, Huawei Li, Xiaowei Li |
| 2016 | DATE | Frequency scheduling for resilient chip multi-processors operating at Near Threshold Voltage. | Ying Wang, Huawei Li, Xiaowei Li |
| 2016 | ICCAD | Re-architecting the on-chip memory sub-system of machine-learning accelerator for embedded devices. | Ying Wang, Huawei Li, Xiaowei Li |
| 2016 | ISCAS | A new countermeasure against scan-based side-channel attacks. | Yanhui Luo, Aijiao Cui, Gang Qu, Huawei Li |
| 2016 | ITC | An accurate algorithm for computing mutation coverage in model checking. | Huina Chao, Huawei Li, Tiancheng Wang, Xiaowei Li, Bo Liu |
| 2016 | VTS | Path constraint solving based test generation for observability-enhanced branch coverage. | Yanhong Zhou, Huawei Li, Tiancheng Wang, Bo Liu, Yingke Gao, Xiaowei Li |
| 2015 | ASPDAC | Enhanced LCCG: A novel test clock generation scheme for faster-than-at-speed delay testing. | Songwei Pei, Ye Geng, Huawei Li, Jun Liu, Song Jin |
| 2015 | DAC | ProPRAM: exploiting the transparent logic resources in non-volatile memory for near data computing. | Ying Wang, Yinhe Han, Lei Zhang, Huawei Li, Xiaowei Li |
| 2015 | DAC | Untitled record | Ying Wang, Yinhe Han, Cheng Wang, Huawei Li, Xiaowei Li |
| 2015 | DATE | Retraining-based timing error mitigation for hardware neural networks. | Jiachao Deng, Yuntan Fang, Zidong Du, Ying Wang, Huawei Li, Olivier Temam, Paolo Ienne, David Novo, Xiaowei Li, Yunji Chen, Chengyong Wu |
| 2015 | DATE | Temperature-aware software-based self-testing for delay faults. | Ying Zhang, Zebo Peng, Jianhui Jiang, Huawei Li, Masahiro Fujita |
| 2015 | ISCAS | A case of precision-tunable STT-RAM memory design for approximate neural network. | Ying Wang, Lili Song, Yinhe Han, Yuanqing Cheng, Huawei Li, Xiaowei Li |
| 2014 | DATE | Functional test generation guided by steady-state probabilities of abstract design. | Jian Wang, Huawei Li, Tao Lv, Tiancheng Wang, Xiaowei Li |
| 2014 | ICCAD | Data-aware DRAM refresh to squeeze the margin of retention time in hybrid memory cube. | Yinhe Han, Ying Wang, Huawei Li, Xiaowei Li |
| 2013 | ISCAS | Enabling Near-Threshold Voltage(NTV) operation in Multi-VDD cache for power reduction. | Yinhe Han, Ying Wang, Huawei Li, Xiaowei Li |
| 2013 | VTS | RSAK: Random stream attack for phase change memory in video applications. | Yuntan Fang, Huawei Li, Xiaowei Li |
| 2011 | DATE | Flex memory: Exploiting and managing abundant off-chip optical bandwidth. | Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li |
| 2011 | ISCA | An abacus turn model for time/space-efficient reconfigurable routing. | Binzhang Fu, Yinhe Han, Jun Ma, Huawei Li, Xiaowei Li |
| 2011 | VTS | A unified test architecture for on-line and off-line delay fault detections. | Songwei Pei, Huawei Li, Xiaowei Li |
| 2010 | ASPDAC | Graph partition based path selection for testing of small delay defects. | Zijian He, Tao Lv, Huawei Li, Xiaowei Li |
| 2010 | DATE | Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs. | Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li |
| 2010 | DATE | An on-chip clock generation scheme for faster-than-at-speed delay testing. | Songwei Pei, Huawei Li, Xiaowei Li |
| 2010 | ITC | On generation of a universal path candidate set containing testable long paths. | Zijian He, Tao Lv, Huawei Li, Xiaowei Li |
| 2010 | ITC | nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications. | Huawei Li, Dawen Xu, Yinhe Han, Kwang-Ting Cheng, Xiaowei Li |
| 2010 | PRDC | Address Remapping for Static NUCA in NoC-Based Degradable Chip-Multiprocessors. | Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li |
| 2010 | VTS | Fast path selection for testing of small delay defects considering path correlations. | Zijian He, Tao Lv, Huawei Li, Xiaowei Li |
| 2009 | PRDC | A New Multiple-Round DOR Routing for 2D Network-on-Chip Meshes. | Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li |
| 2009 | PRDC | Small Delay Fault Simulation for Sequential Circuits. | Li Liu, Jishun Kuang, Huawei Li |
| 2009 | PRDC | Flip-Flop Selection for Transition Test Pattern Reduction Using Partial Enhanced Scan. | Songwei Pei, Huawei Li, Xiaowei Li |
| 2009 | PRDC | Impact of Hazards on Pattern Selection for Small Delay Defects. | Jie Wang, Huawei Li, Yinghua Min, Xiaowei Li, Huaguo Liang |
| 2009 | VTS | Automatic Selection of Internal Observation Signals for Design Verification. | Tao Lv, Huawei Li, Xiaowei Li |
| 2008 | ASPDAC | Robust test generation for power supply noise induced path delay faults. | Xiang Fu, Huawei Li, Yu Hu, Xiaowei Li |
| 2008 | ASPDAC | A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults. | Fei Wang, Yu Hu, Huawei Li, Xiaowei Li |
| 2008 | ITC | Deterministic Diagnostic Pattern Generation (DDPG) for Compound Defects. | Fei Wang, Yu Hu, Huawei Li, Xiaowei Li, Jing Ye, Yu Huang |
| 2008 | VTS | Multiple Coupling Effects Oriented Path Delay Test Generation. | Minjin Zhang, Huawei Li, Xiaowei Li |
| 2008 | VTS | Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects. | Ying Zhang, Huawei Li, Xiaowei Li, Yu Hu |
| 2007 | HCI | A Routing Algorithm for Random Error Tolerance in Network-on-Chip. | Lei Zhang, Huawei Li, Xiaowei Li |
| 2007 | ITC | The design-for-testability features of a general purpose microprocessor. | Da Wang, Xiaoxin Fan, Xiang Fu, Hui Liu, Ke Wen, Rui Li, Huawei Li, Yu Hu, Xiaowei Li |
| 2006 | GLOBECOM | Fast Packet Classification using Group Bit Vector. | Tong Liu, Huawei Li, Xiaowei Li, Yinhe Han |
| 2006 | VTS | Robust Test Generation for Precise Crosstalk-induced Path Delay Faults. | Huawei Li, Pei-Fu Shen, Xiaowei Li |
| 2005 | ASPDAC | Design of an efficient memory subsystem for network processor. | Shuguang Gong, Huawei Li, Yufeng Xu, Tong Liu, Xiaowei Li |
| 2005 | ASPDAC | Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code. | Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li |
| 2005 | PRDC | Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time. | Yu Hu, Xiaowei Li, Huawei Li, Xiaoqing Wen |