| 2011 | DATE | A new reversible design of BCD adder. | Himanshu Thapliyal, N. Ranganathan |
| 2009 | ISCAS | A Strategy for Soft Error Reduction in Multi Core Designs. | Ransford Hyman Jr., Koustav Bhattacharya, N. Ranganathan |
| 2006 | ISLPED | A novel approach for variation aware power minimization during gate sizing. | Venkataraman Mahalingam, N. Ranganathan, Justin E. Harlow III |
| 2006 | ISTAS | Social Fairness in Multi-Emergency Resource Management. | Upavan Gupta, N. Ranganathan |
| 2006 | VLSID | An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition. | Venkataraman Mahalingam, N. Ranganathan |
| 2005 | VLSID | Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks. | Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan |
| 2005 | VLSID | Design of a Low Power Image Watermarking Encoder Using Dual Voltage and Frequency. | Saraju P. Mohanty, N. Ranganathan, Karthikeyan Balakrishnan |
| 2004 | VLSID | Gate Sizing and Buffer Insertion using Economic Models for Power Optimization. | Ashok K. Murugavel, N. Ranganathan |
| 2004 | VLSID | Game Theoretic Modeling of Voltage and Frequency Scaling during Behavioral Synthesis. | Ashok K. Murugavel, N. Ranganathan |
| 2003 | ICCD | Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling. | Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi |
| 2003 | ICCD | A Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power Optimization. | N. Ranganathan, Ashok K. Murugavel |
| 2003 | ISCAS | An ILP-based scheduling scheme for energy efficient high performance datapath synthesis. | Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi |
| 2003 | VLSID | Energy Efficient Scheduling for Datapath Synthesis. | Saraju P. Mohanty, N. Ranganathan |
| 2003 | VLSID | A Framework for Energy and Transient Power Reduction during Behavioral Synthesis. | Saraju P. Mohanty, N. Ranganathan |
| 2003 | VLSID | A Game-Theoretic Approach for Binding in Behavioral Synthesis. | Ashok K. Murugavel, N. Ranganathan |
| 2002 | DAC | Petri net modeling of gate and interconnect delays for power estimation. | Ashok K. Murugavel, N. Ranganathan |
| 2002 | ICCD | Modeling Switching Activity Using Cascaded Bayesian Networks for Correlated Input Streams. | Sanjukta Bhanja, N. Ranganathan |
| 2002 | ISLPED | Power estimation of sequential circuits using hierarchical colored hardware petri net modeling. | Ashok K. Murugavel, N. Ranganathan |
| 2002 | VLSID | Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks. | Sanjukta Bhanja, N. Ranganathan |
| 2002 | VLSID | A Real Delay Switching Activity Simulator Based on Petri Net Modeling. | Ashok K. Murugavel, N. Ranganathan |
| 2001 | DAC | Dependency Preserving Probabilistic Modeling of Switching Activity using Bayesian Networks. | Sanjukta Bhanja, N. Ranganathan |
| 2001 | VLSID | Average Power in Digital CMOS Circuits using Least Square Estimation. | Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali |
| 2000 | HCW | New Cost Metrics for Iterative Task Assignment Algorithms in Heterogeneous Computing Systems. | Raju D. Venkataramana, N. Ranganathan |
| 2000 | VLSID | Design Partitioning on Single-Chip Emulation Systems. | Abdel Ejnioui, N. Ranganathan |
| 2000 | VLSID | Routing on Switch Matrix Multi-FPGA Systems. | Abdel Ejnioui, N. Ranganathan |
| 2000 | VLSID | CREAM: Combined Register and Module Assignment with Floorplanning for Low Power Datapath Synthesis. | Vamsi K. Srikantam, N. Ranganathan, Srikanth Srinivasan |
| 1999 | FPGA | Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems. | Abdel Ejnioui, N. Ranganathan |
| 1999 | HCW | Multiple Cost Optimization for Task Assignment in Heterogeneous Computing Systems Using Learning Automata. | Raju D. Venkataramana, N. Ranganathan |
| 1999 | ISCAS | Context based lossless intraframe coding of video sequence using embedded zerotree wavelets. | Veeru N. Ramaswamy, Kameswara Rao Namuduri, N. Ranganathan |
| 1999 | SAC | A Learning Automata Based Framework for Task Assignment in Heterogeneous Computing Systems. | Raju D. Venkataramana, N. Ranganathan |
| 1999 | VLSID | Energy Efficient Datapath Synthesis Using Dynamic Frequency Clocking and Multiple Voltages. | Vamsi Krishna, N. Ranganathan, Narayanan Vijaykrishnan |
| 1998 | DCC | Empirical Channel Matched Quantizer Design and UEP for Robust Image Transmission. | Ramamurti Chandramouli, N. Ranganathan, Shivaraman J. Ramadoss |
| 1998 | ECOOP | Object-Oriented Architectural Support for a Java Processor. | Narayanan Vijaykrishnan, N. Ranganathan, Ravi Gadekarla |
| 1998 | ICCD | A simple adaptive wormhole routing algorithm for MIMD systems. | Raju D. Venkataramana, N. Ranganathan |
| 1998 | ICIP | Joint Optimization of Quantization and On-Line Channel Estimation for Low Bit-Rate Video Transmission. | Ramamurti Chandramouli, Sharad Kumar, N. Ranganathan |
| 1998 | SMC | Rate control for a video coder using learning automata. | Ramamurti Chandramouli, Sharad Kumar, N. Ranganathan |
| 1998 | VLSID | Computation of Lower and Upper Bounds for Switching Activity: A Unified Approach. | Vamsi Krishna, Ramamurti Chandramouli, N. Ranganathan |
| 1997 | ICCD | Effect of Message Length and Processor Speed on the Performance of the Bidirectional Ring-Based Multiprocessor. | Hitoshi Oi, N. Ranganathan |
| 1997 | ICIP | Performance Analysis of Wavelets in Embedded Zerotree-Based Lossless Image Coding Schemes. | Veeru N. Ramaswamy, Kameswara Rao Namuduri, N. Ranganathan |
| 1997 | VLSID | C3L: A Chip for Connected Component Labeling. | Ashley Rasquinha, N. Ranganathan |
| 1996 | ICCD | A VLSI chip for image compression using variable block size segmentation. | S. B. Aruru, N. Ranganathan, Kameswara Rao Namuduri |
| 1996 | ICCD | A VLSI array architecture with dynamic frequency clocking. | N. Ranganathan, Narayanan Vijaykrishnan, N. Bhavanishankar |
| 1996 | ICPR | SIMD algorithms for single link and complete link pattern clustering. | S. Arumugavelu, N. Ranganathan |
| 1996 | ICPR | A VLSI system architecture for lossless image compression. | S. B. Aruru, N. Ranganathan, Kameswara Rao Namuduri |
| 1996 | ICPR | SVBS: a high-resolution medical image compression algorithm using slicing with variable block size segmentation. | Kameswara Rao Namuduri, N. Ranganathan, Hooman Rashedi |
| 1996 | ICPR | Lossless image compression using wavelet decomposition. | Veeru N. Ramaswamy, Kameswara Rao Namuduri, N. Ranganathan |
| 1996 | ICPR | A dynamic frequency linear array processor for image processing. | N. Ranganathan, N. Bhavanishankar, Narayanan Vijaykrishnan |
| 1996 | VLSID | A tree matching chip. | Vamsi Krishna, Abdel Ejnioui, N. Ranganathan |
| 1996 | VLSID | SUBGEN: a genetic approach for subcircuit extraction. | Narayanan Vijaykrishnan, N. Ranganathan |
| 1995 | DATE | A prototype VLSI chip architecture for JPEG image compression. | Mario Kovac, N. Ranganathan, Martin Zagar |
| 1995 | HPCA | A VLSI Architecture for Computer the Tree-to-Tree Distance. | Raghu Sastry, N. Ranganathan |
| 1995 | ICCD | Systolic algorithms for tree pattern matching. | Abdel Ejnioui, N. Ranganathan |
| 1995 | VLSID | JAGUAR: a high speed VLSI chip for JPEG image compression standard. | Mario Kovac, N. Ranganathan |
| 1994 | ICCD | A VLSI Chip for Template Matching. | N. Ranganathan, Satish Venugopal |
| 1994 | ICPP | An Efficient VLSI Architecture for Template Matching. | N. Ranganathan, Satish Venugopal |
| 1994 | ICPR | A lossless image compression algorithm using variable block size segmentation. | N. Ranganathan, Steve G. Romaniuk, Kameswara Rao Namuduri |
| 1994 | ICPR | An efficient VLSI architecture for template matching based on moment preserving pattern matching. | N. Ranganathan, Satish Venugopal |
| 1994 | VLSID | ACE: A VLSI Chip for Galois Field GF (2 | Mario Kovac, N. Ranganathan |
| 1993 | ICCD | SMAC: A Scene Matching Chip. | N. Ranganathan, Raghu Sastry, Raguveer Venkatesan, Joseph W. Yoder, David C. Keezer |
| 1993 | ICCD | A Systolic Array for Approximate String Matching. | Raghu Sastry, N. Ranganathan |
| 1993 | ICRA | A Model for Determining Sensor Confidence. | Ken Hughes, N. Ranganathan |
| 1993 | VLSID | SIGMA: A VLSI Chip for Galois Field GF(2 | Mario Kovac, N. Ranganathan, M. Varanasi |
| 1993 | VLSID | Hardware Algorithms for Polygon Matching. | Raghu Sastry, N. Ranganathan, Horst Bunke |
| 1992 | ICCD | MARVLE: A VLSI Chip for Variable Length Encoding and Decoding. | Amar Mukherjee, Jeffrey W. Flieder, N. Ranganathan |
| 1992 | ICPR | Edge detection models based on Gabor filters. | Kameswara Rao Namuduri, Rajiv Mehrotra, N. Ranganathan |
| 1992 | ICPR | SIBA: a VLSI systolic array chip for image processing. | Minesh I. Patel, Patrick McCabe, N. Ranganathan |
| 1992 | ICPR | A VLSI hardware accelerator for dynamic time warping. | V. K. Sundaresan, Sanjay Nichani, N. Ranganathan, Ravi Sankar |
| 1992 | ICPR | A VLSI architecture for hierarchical scene matching. | R. Venkatesan, Raghu Sastry, N. Ranganathan |
| 1992 | IROS | trulla : An Algorithm For Path Planning Among Weighted Regions By Localized Propagations. | Ken Hughes, Alade Tokuta, N. Ranganathan |
| 1992 | VLSID | A CMOS VLSI Chip for Motion Detection. | N. Ranganathan, Rajiv Mehrotra, S. Kurji |
| 1992 | VLSID | A Two-dimensional Systolic Array Processor for Image Processing. | N. Ranganathan, Minesh I. Patel, Patrick McCabe |
| 1991 | ICASSP | An architecture to implement multiresolution. | N. Ranganathan, Rajiv Mehrotra, Kameswara Rao Namuduri |
| 1990 | ICCD | SAP: design of a systolic array processor for computation in vision. | Sanjay Nichani, N. Ranganathan |
| 1990 | ICPR | Fast spatiotemporal filters. | K. R. Namaduri, Rajiv Mehrotra, N. Ranganathan |
| 1990 | ICPR | A VLSI architecture for difference picture-based dynamic scene analysis. | N. Ranganathan, Rajiv Mehrotra |
| 1989 | ICCD | Adaptive and pipelined VLSI designs for tree-based codes. | Amar Mukherjee, N. Ranganathan, Mostafa A. Bassiouni |
| 1989 | ICDE | On Software and Hardware Techniques of Data Engineering. | Mostafa A. Bassiouni, Amar Mukherjee, N. Ranganathan |
| 1989 | ICTAI | A VLSI system for difference picture-based motion analysis. | N. Ranganathan, Rajiv Mehrotra |
| 1988 | SC | A scheme for data compression in supercomputers. | Mostafa A. Bassiouni, N. Ranganathan, Amar Mukherjee |
| 1988 | SSDBM | Software and Hardware Enhancement of Arithmetic Coding. | Mostafa A. Bassiouni, N. Ranganathan, Amar Mukherjee |