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Norbert Wehn

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

138

Venues

34

Active years

1987–2026

Best venue rank

A*

Where they publish

Papers

138 indexed papers, newest first.

YearVenueTitleAuthors
2026DATEMicroscaling-Stochastic Computing Based Systolic Arrays for Energy-Efficient Deep Neural Network Inference.Mohammad Hassani Sadi, Bilal Hammoud, Norbert Wehn
2026DATEMulti-Partner Project: A Holistic and Open-Source Approach to Efficient, Secure and Reliable AI Hardware Deployment in DI-EDAI.Georgios Sotiropoulos, Felix Frombach, Julian Hfer, Tanja Harbaum, Jrgen Becker, Henrik Iver Thore, Vincent Meyers, Mehdi B. Tahoori, Zeynep Demirdag, Mohammed Bakr Sikal, Hassan Nassar, Heba Khdr, Jrg Henkel, Christopher Wolters, Philipp van Kempen, Johannes Geier, Ulf Schlichtmann, Batuhan Sesli, Muhammad Sabih, Jakob Wittmann, Frank Hannig, Jrgen Teich, Lukas Steiner, Norbert Wehn, Mohamed Shelkamy Ali, Philipp Schmitz, Wolfgang Kunz, Stefan Koegler, Georg Sigl
2026ISCASFrom RTL to Prompt Coding: Empowering the Next Generation of Chip Designers through LLMs.Lukas Krupp, Matthew Venn, Norbert Wehn
2025DATEMulti-Partner Project: Sustainable Textile Electronics (STELEC).Bo Zhou, Mengxi Liu, Sizhen Bian, Daniel Geiler, Paul Lukowicz, Jos Miranda, Jonathan Dan, David Atienza, Mohamed Amine Riahi, Norbert Wehn, Russel N. Torah, Sheng Yong, Jidong Liu, Stephen P. Beeby, Magdalena Kohler, Berit Greinke, Junchun Yu, Vincent Nierstrasz, Leila Sheldrick, Rebecca Stewart, Tommaso Nieri, Matteo Maccanti, Daniele S. Spinelli
2025DATEImproving Chip Design Enablement for Universities in Europe - A Position Paper.Lukas Krupp, Ian O'Connor, Luca Benini, Christoph Studer, Joachim Rodrigues, Norbert Wehn
2025DATEMulti-Partner Project: Open-Source Design Tools for Co-Development of AI Algorithms and AI Chips: (Initial Stage).Mehdi B. Tahoori, Jrgen Becker, Jrg Henkel, Wolfgang Kunz, Ulf Schlichtmann, Georg Sigl, Jrgen Teich, Norbert Wehn
2025DDECSDesign of a Low-Power 4.3 Gb/s Transceiver Using Pre-computed Lookup Tables.Hussien Abdo, Jan Lappas, Mohammadreza Esmaeilpour, Christian Weis, Norbert Wehn
2025ETSAnalysis and Mitigation of Radiation Effects in SRAM-based Register Files.Zhe Zhang, Surendra Hemaram, Mahta Mayahinia, Christian Weis, Norbert Wehn, Mehdi B. Tahoori, Sani R. Nassif, Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian
2025ISCASMachine Learning for Improving Timing Accuracy.Mohamed Amine Riahi, Sani R. Nassif, Norbert Wehn
2024ACSSCChannel Coding Under Silicon Implementation Constraints.Oliver Griebel, Lucas Johannsen, Claus Kestel, Matthias Herrmann, Norbert Wehn
2024ASPDACTiming Analysis beyond Complementary CMOS Logic Styles.Jan Lappas, Mohamed Amine Riahi, Christian Weis, Norbert Wehn, Sani R. Nassif
2024DATEA Mapping of Triangular Block Interleavers to DRAM for Optical Satellite Communication.Lukas Steiner, Timo Lehnigk-Emden, Markus Fehrenz, Norbert Wehn
2024DSDAchieving High Throughput with a Trainable Neural-Network-Based Equalizer for Communications on FPGA.Jonas Ney, Norbert Wehn
2024ETSError Detection and Correction Codes for Safe In-Memory Computations.Luca Parrini, Taha Soliman, Benjamin Hettwer, Jan Micha Borrmann, Simranjeet Singh, Ankit Bende, Vikas Rana, Farhad Merchant, Norbert Wehn
2024IOLTSDo Radiation and Aging Impact DVFS? TCAD-based Analysis on 22 nm FDSOI Latches.Zhe Zhang, Christian Weis, Norbert Wehn, Mehdi B. Tahoori, Sani R. Nassif
2024IGARSSFPGA Onboard Processing of Tiny-ML Models Using Radar-Sensing for Oil Spill Monitoring.Bilal Hammoud, Jonas Ney, Charbel Bou-Mosleh, Norbert Wehn
2024IGARSSRadar Backscattering Sensitivity to Emulsions Using Spectral Analysis from Nadir-Aerial Response Systems.Bilal Hammoud, Norbert Wehn
2024ITCTesting for aging in advanced SRAM: From front end of the line transistors to back end of the line interconnects.Zhe Zhang, Mahta Mayahinia, Christian Weis, Norbert Wehn, Mehdi B. Tahoori, Sani R. Nassif, Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian
2024VTSAddressing the Combined Effect of Transistor and Interconnect Aging in SRAM towards Silicon Lifecycle Management.Zhe Zhang, Mahta Mayahinia, Christian Weis, Norbert Wehn, Mehdi B. Tahoori, Sani R. Nassif, Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian
2023DATEZuSE Ki-Avf: Application-Specific AI Processor for Intelligent Sensor Signal Processing in Autonomous Driving.Gia Bao Thieu, Sven Gesper, Guillermo Pay-Vay, Christoph Riggers, Oliver Renke, Till Fiedler, Jakob Marten, Tobias Stuckenberg, Holger Blume, Christian Weis, Lukas Steiner, Chirag Sudarshan, Norbert Wehn, Lennart M. Reimann, Rainer Leupers, Michael Beyer, Daniel Khler, Alisa Jauch, Jan Micha Borrmann, Setareh Jaberansari, Tim Berthold, Meinolf Blawat, Markus Kock, Gregor Schewior, Jens Benndorf, Frederik Kautz, Hans-Martin Blthgen, Christian Sauer
2023IOLTSA Learning-Based Approach for Single Event Transient Analysis in Pass Transistor Logic.Zhe Zhang, Zhihang Wu, Christian Weis, Norbert Wehn, Mehdi Baradaran Tahoori
2023IGARSSOil Spill Detection in Calm Ocean Conditions: A U-Net Model Novel Solution.Bilal Hammoud, Charbel Bou-Mosleh, Mohamed Moursi, Norbert Wehn
2023IGARSSA Novel Iterative Estimation Technique Using Radar Sensing to Remotely Characterize Oil Slicks During Spills.Bilal Hammoud, Norbert Wehn
2022DATERevisiting Pass-Transistor Logic Styles in a 12nm FinFET Technology Node.Jan Lappas, Andr Lucas Chinazzo, Christian Weis, Chenyang Xia, Zhihang Wu, Leibin Ni, Norbert Wehn
2022ETSMachine learning based soft error rate estimation of pass transistor logic in high-speed communication.Zhe Zhang, Jan Lappas, Andr Lucas Chinazzo, Christian Weis, Zhihang Wu, Leibin Ni, Norbert Wehn, Mehdi B. Tahoori
2022FPGAFPGA-based Trainable Autoencoder for Communication Systems.Jonas Ney, Sebastian Drner, Matthias Herrmann, Mohammad Hassani Sadi, Jannis Clausius, Stephan ten Brink, Norbert Wehn
2022GLOBECOMBlind and Channel-agnostic Equalization Using Adversarial Networks.Vincent Lauinger, Manuel Hoffmann, Jonas Ney, Norbert Wehn, Laurent Schmalen
2022ISCASOptimization of DRAM based PIM Architecture for Energy-Efficient Deep Neural Network Training.Chirag Sudarshan, Mohammad Hassani Sadi, Christian Weis, Norbert Wehn
2022IGARSSA Maximum A-Posteriori Probabilistic Approach using UAV-Nadir-Looking Wide-Band Radar for Remote Sensing Oil-Spill Detection.Bilal Hammoud, Norbert Wehn
2021ASPDACA Novel DRAM-Based Process-in-Memory Architecture and its Implementation for CNNs.Chirag Sudarshan, Taha Soliman, Cecilia De la Parra, Christian Weis, Leonardo Ecco, Matthias Jung, Norbert Wehn, Andre Guntoro
2021DICTABurnt Forest Estimation from Sentinel-2 Imagery of Australia using Unsupervised Deep Learning.Nosheen Abid, Muhammad Imran Malik, Muhammad Shahzad, Faisal Shafait, Haider Ali, Muhammad Mohsin Ghaffar, Christian Weis, Norbert Wehn, Marcus Liwicki
2021DICTAQuantYOLO: A High-Throughput and Power-Efficient Object Detection Network for Resource and Power Constrained UAVs.Muhammad Gohar Javed, Minahil Raza, Muhammad Mohsin Ghaffar, Christian Weis, Norbert Wehn, Muhammad Shahzad, Faisal Shafait
2021FPLHALF: Holistic Auto Machine Learning for FPGAs.Jonas Ney, Dominik Marek Loroch, Vladimir Rybalkin, Nico Weber, Jens Krger, Norbert Wehn
2021ICASSPADMM-Based ML Decoding: from Theory to Practice.Kira Kraft, Norbert Wehn
2021ISCASExploiting Resiliency for Kernel-Wise CNN Approximation Enabled by Adaptive Hardware Design.Cecilia De la Parra, Ahmed El-Yamany, Taha Soliman, Akash Kumar, Norbert Wehn, Andre Guntoro
2020CCGRIDAnalysis and Optimization of TLS-based Security Mechanisms for Low Power IoT Systems.Frederik Lauer, Carl Christian Rheinlnder, Claus Kestel, Norbert Wehn
2020DATEFast and Accurate DRAM Simulation: Can we Further Accelerate it?Johannes Feldmann, Kira Kraft, Lukas Steiner, Norbert Wehn, Matthias Jung
2020DATETLS-Level Security for Low Power Industrial IoT Network Infrastructures.Jochen Mades, Gerd Ebelt, Boris Janjic, Frederik Lauer, Carl Christian Rheinlnder, Norbert Wehn
2020FPGAWhen Massive GPU Parallelism Ain't Enough: A Novel Hardware Architecture of 2D-LSTM Neural Network.Vladimir Rybalkin, Norbert Wehn
2020ICASSPFully Pipelined Iteration Unrolled Decoders the Road to TB/S Turbo Decoding.Stefan Weithoffer, Rami Klaimi, Charbel Abdel Nour, Norbert Wehn, Catherine Douillard
2020ISCASAccess-Aware Per-Bank DRAM Refresh for Reduced DRAM Refresh Overhead.der F. Zulian, Christian Weis, Norbert Wehn
2020PIMRCA 506Gbit/s Polar Successive Cancellation List Decoder with CRC.Claus Kestel, Lucas Johannsen, Oliver Griebel, Jhon Jimenez, Timo Vogt, Timo Lehnigk-Emden, Norbert Wehn
2020PIMRCLow-complexity Computational Units for the Local-SOVA Decoding Algorithm.Stefan Weithoffer, Rami Klaimi, Charbel Abdel Nour, Norbert Wehn, Catherine Douillard
2020WCNCAdvanced Hardware Architectures for Turbo Code Decoding Beyond 100 Gb/s.Stefan Weithoffer, Oliver Griebel, Rami Klaimi, Charbel Abdel Nour, Norbert Wehn
2019DATESpeculative Temporal Decoupling Using fork().Matthias Jung, Frank Schnicke, Markus Damm, Thomas Kuhn, Norbert Wehn
2019DATEPolar Code Decoder Framework.Timo Lehnigk-Emden, Matthias Alles, Claus Kestel, Norbert Wehn
2019ISCASAn In-DRAM Neural Network Processing Engine.Chirag Sudarshan, Jan Lappas, Muhammad Mohsin Ghaffar, Vladimir Rybalkin, Christian Weis, Matthias Jung, Norbert Wehn
2019RedundancyChannel Models for Physical Unclonable Functions based on DRAM Retention Measurements.Sven Melich, Sebastian Bitzer, Chirag Sudarshan, Christian Weis, Norbert Wehn, Martin Bossert, Robert F. H. Fischer
2018DATEImproving the error behavior of DRAM by exploiting its Z-channel property.Kira Kraft, Chirag Sudarshan, Deepak M. Mathew, Christian Weis, Norbert Wehn, Matthias Jung
2018DATEThe transprecision computing paradigm: Concept, design, and applications.A. Cristiano I. Malossi, Michael Schaffner, Anca Molnos, Luca Gammaitoni, Giuseppe Tagliavini, Andrew P. J. Emerson, Andrs Toms, Dimitrios S. Nikolopoulos, Eric Flamand, Norbert Wehn
2018DATEAn analysis on retention error behavior and power consumption of recent DDR4 DRAMs.Deepak M. Mathew, Martin Schultheis, Carl Christian Rheinlnder, Chirag Sudarshan, Christian Weis, Norbert Wehn, Matthias Jung
2018DocEngiDocChip: A Configurable Hardware Architecture for Historical Document Image Processing: Percentile Based Binarization.Vladimir Rybalkin, Syed Saqib Bukhari, Muhammad Mohsin Ghaffar, Aqib Ghafoor, Norbert Wehn, Andreas Dengel
2018FPLFINN-L: Library Extensions and Design Trade-Off Analysis for Variable Precision LSTM Networks on FPGAs.Vladimir Rybalkin, Alessandro Pappalardo, Muhammad Mohsin Ghaffar, Giulio Gambardella, Norbert Wehn, Michaela Blott
2018ISCASThe Role of Memories in Transprecision Computing.Christian Weis, Matthias Jung, der F. Zulian, Chirag Sudarshan, Deepak M. Mathew, Norbert Wehn
2018RVA Framework for Non-intrusive Trace-driven Simulation of Manycore Architectures with Dynamic Tracing Configuration.Jasmin Jahic, Matthias Jung, Thomas Kuhn, Claus Kestel, Norbert Wehn
2017DACA Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications.Sebastian Haas, Tobias Seifert, Benedikt Nthen, Stefan Scholze, Sebastian Hppner, Andreas Dixius, Esther Prez Adeva, Thomas R. Augustin, Friedrich Pauls, Sadia Moriam, Mattis Hasler, Erik Fischer, Yong Chen, Emil Mats, Georg Ellguth, Stephan Hartmann, Stefan Schiefer, Love Cederstrm, Dennis Walter, Stephan Henker, Stefan Hnzsche, Johannes Uhlig, Holger Eisenreich, Stefan Weithoffer, Norbert Wehn, Ren Schffny, Christian Mayr, Gerhard P. Fettweis
2017DATEHardware architecture of Bidirectional Long Short-Term Memory Neural Network for Optical Character Recognition.Vladimir Rybalkin, Norbert Wehn, Mohammad Reza Yousefi, Didier Stricker
2017DATEAn advanced embedded architecture for connected component analysis in industrial applications.Menbere Tekleyohannes, MohammadSadegh Sadri, Christian Weis, Norbert Wehn, Martin Klein, Michael Siegrist
2017SCTensorQuant: A Simulation Toolbox for Deep Neural Network Quantization.Dominik Marek Loroch, Franz-Josef Pfreundt, Norbert Wehn, Janis Keuper
2017SCReal-Time Financial Risk Measurement of Dynamic Complex Portfolios with Python and PyOpenCL.Javier Alejandro Varela, Norbert Wehn, Sascha Desmettre, Ralf Korn
2016ASPDACEfficient reliability management in SoCs - an approximate DRAM perspective.Matthias Jung, Deepak M. Mathew, Christian Weis, Norbert Wehn
2016DACInvited - Approximate computing with partially unreliable dynamic random access memory - approximate DRAM.Matthias Jung, Deepak M. Mathew, Christian Weis, Norbert Wehn
2016DATEError resilience and energy efficiency: An LDPC decoder design study.Philipp Schlfer, Chu-Hsiang Huang, Clayton Schoeny, Christian Weis, Yao Li, Norbert Wehn, Lara Dolecek
2016DATESaturated min-sum decoding: An "afterburner" for LDPC decoder hardware.Stefan Scholl, Philipp Schlfer, Norbert Wehn
2016VTCA New Architecture for High Speed, Low Latency NB-LDPC Check Node Processing for GF(256).Vladimir Rybalkin, Philipp Schlfer, Norbert Wehn
2015DATEReverse longstaff-schwartz american option pricing on hybrid CPU/FPGA systems.Christian Brugger, Javier Alejandro Varela, Norbert Wehn, Songyin Tang, Ralf Korn
2015DATERetention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs.Christian Weis, Matthias Jung, Peter Ehses, Cristiano Santos, Pascal Vivet, Sven Goossens, Martijn Koedam, Norbert Wehn
2015PIMRCA new architecture for high throughput, low latency NB-LDPC check node processing.Philipp Schlfer, Vladimir Rybalkin, Norbert Wehn, Matthias Alles, Timo Lehnigk-Emden, Emmanuel Boutillon
2015PIMRCLatency reduction for LTE/LTE-A turbo-code decoders by on-the-fly calculation of CRC.Stefan Weithoffer, Norbert Wehn
2015SCOptimization strategies for portable code for Monte Carlo-based value-at-risk systems.Javier Alejandro Varela, Claus Kestel, Christian de Schryver, Norbert Wehn, Sascha Desmettre, Ralf Korn
2014DATEExploiting expendable process-margins in DRAMs for run-time performance optimization.Karthik Chandrasekar, Sven Goossens, Christian Weis, Martijn Koedam, Benny Akesson, Norbert Wehn, Kees Goossens
2014DATETechnology transfer towards Horizon 2020.Rainer Leupers, Norbert Wehn, Marco Roodzant, Johannes Stahl, Luca Fanucci, Albert Cohen, Bernd Janson
2014DATEEnergy optimization in 3D MPSoCs with Wide-I/O DRAM using temperature variation aware bank-wise refresh.MohammadSadegh Sadri, Matthias Jung, Christian Weis, Norbert Wehn, Luca Benini
2014DATEConnecting different worlds - Technology abstraction for reliability-aware design and Test.Ulf Schlichtmann, Veit Kleeberger, Jacob A. Abraham, Adrian Evans, Christina Gimmler-Dumont, Michael Gla, Andreas Herkersdorf, Sani R. Nassif, Norbert Wehn
2014DATEHardware implementation of a Reed-Solomon soft decoder based on information set decoding.Stefan Scholl, Norbert Wehn
2014DDECSA new architecture for minimum mean square error sorted QR decomposition for MIMO wireless communication systems.Victor Tomashevich, Christina Gimmler-Dumont, Christian Fesl, Norbert Wehn, Ilia Polian
2014FPLHyPER: A runtime reconfigurable architecture for monte carlo option pricing in the Heston model.Christian Brugger, Christian de Schryver, Norbert Wehn
2014PIMRCA simplex algorithm for LP decoding hardware.Florian Gensheimer, Stefan Ruzika, Stefan Scholl, Norbert Wehn
2014SCA systematic methodology for analyzing closed-form Heston pricer regarding their accuracy and runtime.Christian Brugger, Gongda Liu, Christian de Schryver, Norbert Wehn
2013APCCCode-aided synchronization with QPSK, 8-PSK and 16-QAM modulations.Imran Ali, Uwe Wasenmller, Norbert Wehn
2013DACTowards variation-aware system-level power estimation of DRAMs: an empirical approach.Karthik Chandrasekar, Christian Weis, Benny Akesson, Norbert Wehn, Kees Goossens
2013DACReliable on-chip systems in the nano-era: lessons learnt and future trends.Jrg Henkel, Lars Bauer, Nikil D. Dutt, Puneet Gupta, Sani R. Nassif, Muhammad Shafique, Mehdi Baradaran Tahoori, Norbert Wehn
2013DATESystem and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs.Karthik Chandrasekar, Christian Weis, Benny Akesson, Norbert Wehn, Kees Goossens
2013DATEA multi-level Monte Carlo FPGA accelerator for option pricing in the Heston model.Christian de Schryver, Pedro Torruella, Norbert Wehn
2012DATEDRAM selection and configuration for real-time mobile systems.Manil Dev Gomony, Christian Weis, Benny Akesson, Norbert Wehn, Kees Goossens
2012DATEAn energy efficient DRAM subsystem for 3D integrated SoCs.Christian Weis, Igor Loi, Luca Benini, Norbert Wehn
2012DCCA Parallel Adaptive Range Coding Compressor: Algorithm, FPGA Prototype, Evaluation.Ivan Shcherbakov, Norbert Wehn
2012ETSDependable embedded systems: The German research foundation DFG priority program SPP 1500.Jrg Henkel, Oliver Bringmann, Andreas Herkersdorf, Wolfgang Rosenstiel, Norbert Wehn
2011DATEDesign space exploration for 3D-stacked DRAMs.Christian Weis, Norbert Wehn, Igor Loi, Luca Benini
2011FDLBringing C++ productivity to VHDL world: From language definition to a case study.Ivan Shcherbakov, Christian Weis, Norbert Wehn
2011KESEnergy Efficient Acceleration and Evaluation of Financial Computations towards Real-Time Pricing.Christian de Schryver, Matthias Jung, Norbert Wehn, Henning Marxen, Anton Kostiuk, Ralf Korn
2011SCAlgorithmic complexity in the heston model: an implementation view.Henning Marxen, Anton Kostiuk, Ralf Korn, Christian de Schryver, Stephan Wurm, Ivan Shcherbakov, Norbert Wehn
2011RSPValidation of channel decoding ASIPs a case study.Christian Brehm, Norbert Wehn, Sacha Loitz, Wolfgang Kunz
2010DATEA 150Mbit/s 3GPP LTE Turbo code decoder.Matthias May, Thomas Ilnseher, Norbert Wehn, Wolfgang Raab
2010DATEA rapid prototyping system for error-resilient multi-processor systems-on-chip.Matthias May, Norbert Wehn, Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Daniel Ziener, Jrgen Teich
2010FDLComplete Verification of Weakly Programmable IPs against Their Operational ISA Model.Sacha Loitz, Markus Wedler, Dominik Stoffel, Christian Brehm, Norbert Wehn, Wolfgang Kunz
2010ISCASFully integrated UWB impulse transmitter and 402-to-405MHz super-regenerative receiver for medical implant devices.Muhammad Anis, Maurits Ortmanns, Norbert Wehn
2010MobiquitousAmICA - A Flexible, Compact, Easy-to-Program and Low-Power WSN Platform.Sebastian Wille, Norbert Wehn, Ivan Martinovic, Simon Kunz, Peter Ghner
2010PIMRCLow-complexity iteration control for MIMO-BICM systems.Christina Gimmler, Timo Lehnigk-Emden, Norbert Wehn
2009DATEError correction in single-hop wireless sensor networks - A case study.Daniel Schmidt, Matthias Berning, Norbert Wehn
2009DATEA novel LDPC decoder for DVB-S2 IP.Stefan Mller, Manuel Schreger, Marten Kabutz, Matthias Alles, Frank Kienle, Norbert Wehn
2009ISITValid inequalities for binary linear codes.Stefan Ruzika, Akin Tanatmis, Frank Kienle, Horst W. Hamacher, Norbert Wehn, Mayur Punekar
2008DATEA Case Study in Reliability-Aware Design: A Resilient LDPC Code Decoder.Matthias May, Matthias Alles, Norbert Wehn
2008DATEA Reconfigurable Application Specific Instruction Set Processor for Convolutional and Turbo Decoding in a SDR Environment.Timo Vogt, Norbert Wehn
2008FPLApplication-specific reconfigurable processors.Heiko Hinkelmann, Peter Zipf, Manfred Glesner, Matthias Alles, Timo Vogt, Norbert Wehn, Gtz Kappen, Tobias G. Noll
2008ISCAS3.1-to-7GHz UWB impulse radio transceiver front-end based on statistical correlation technique.Muhammad Anis, Reinhard Tielert, Norbert Wehn
2008VTCMacro Interleaver Design for Bit Interleaved Coded Modulation with Low-Density Parity-Check Codes.Frank Kienle, Norbert Wehn
2007DATELow complexity LDPC code decoders for next generation standards.Torben Brack, Matthias Alles, Timo Lehnigk-Emden, Frank Kienle, Norbert Wehn, Nicola E. L'Insalata, Francesco Rossi, Massimo Rovini, Luca Fanucci
2007ISCASEvaluation of High Throughput Turbo-Decoder Architectures.Matthias May, Christian Neeb, Norbert Wehn
2007PIMRCImplementation Issues of Turbo Synchronization with Duo-Binary Turbo Decoding.Matthias Alles, Timo Lehnigk-Emden, Uwe Wasenmller, Norbert Wehn
2007VTCA Reliability-Aware LDPC Code Decoding Algorithm.Matthias Alles, Torben Brack, Norbert Wehn
2007VTCA Survey on LDPC Codes and Decoders for OFDM-based UWB Systems.Torben Brack, Matthias Alles, Timo Lehnigk-Emden, Frank Kienle, Norbert Wehn, Friedbert Berens, Andreas Ruegg
2006DATEDisclosing the LDPC code decoder design space.Torben Brack, Frank Kienle, Norbert Wehn
2006DSDDesigning Efficient Irregular Networks for Heterogeneous Systems-on-Chip.Christian Neeb, Norbert Wehn
2006PIMRCA Synthesizable IP Core for WIMAX 802.16E LDPC Code Decoding.Torben Brack, Matthias Alles, Frank Kienle, Norbert Wehn
2006VTCFast convergence algorithm for LDPC Codes.Frank Kienle, Timo Lehnigk-Emden, Norbert Wehn
2005DATEA Synthesizable IP Core for DVB-S2 LDPC Code Decoding.Frank Kienle, Torben Brack, Norbert Wehn
2005GIEnergieminimierung von Basisbandsignalverarbeitungsalgorithmen auf programmierbaren Plattformen.Christian Neeb, Norbert Wehn
2005ISCASNetwork-on-chip-centric approach to interleaving in high throughput channel decoders.Christian Neeb, Michael J. Thul, Norbert Wehn
2004ASPDACDesign methodology for IRA codes.Frank Kienle, Norbert Wehn
2004DATEChannel Decoder Architecture for 3G Mobile Wireless Terminals.Friedbert Berens, Gerd Kreiselmaier, Norbert Wehn
2004ICASSPJoint graph-decoder design of IRA codes on scalable architectures [LDPC codes].Frank Kienle, Norbert Wehn
2003DATECommunication Centric Architectures for Turbo-Decoding on Embedded Multiprocessors .Frank Gilbert, Michael J. Thul, Norbert Wehn
2003ICASSPVLSI-implementation issues of turbo trellis-coded modulation.Frank Kienle, Gerd Kreiselmaier, Norbert Wehn
2003ICASSPConcurrent interleaving architectures for high-throughput channel coding.Michael J. Thul, Frank Gilbert, Norbert Wehn
2002DATEHardware/Software Trade-Offs for Advanced 3G Channel Coding.Heiko Michel, Alexander Worm, Norbert Wehn, Michael Mnch
2002ICASSPEvaluation of algorithm optimizations for low-power Turbo-Decoder implementations.Michael J. Thul, Timo Vogt, Frank Gilbert, Norbert Wehn
2002ISCASEnabling high-speed turbo-decoding through concurrent interleaving.Michael J. Thul, Norbert Wehn, L. P. Rao
2001ASPDACLow power implementation of a turbo-decoder on programmable architectures.Frank Gilbert, Alexander Worm, Norbert Wehn
2001DATEDesign of low-power high-speed maximum a priori decoder architectures.Alexander Worm, Holger Lamm, Norbert Wehn
2001VLSIDEmbedded Memories in System Design: Technology, Application, Design and Tools.Doris Keitel-Schulz, Norbert Wehn, Francky Catthoor, Preeti Ranjan Panda
2001VLSIDVlsi Architectures For High-Speed Map Decoders.Alexander Worm, Holger Lamm, Norbert Wehn
2000DATEAutomating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths.Michael Mnch, Norbert Wehn, Bernd Wurth, Renu Mehra, Jim Sproch
1998DATEEmbedded DRAM Architectural Trade-Offs.Norbert Wehn, Sren Hein
1995FPLAdvanced Method for Industry Related Education with an FPGA Design Self-Learning Kit.U. Zahm, Thomas Hollstein, Hans-Jrgen Herpel, Norbert Wehn, Manfred Glesner
1991RSPRAMSES-a rapid prototyping environment for embedded control applications.Hans-Jrgen Herpel, Norbert Wehn, Manfred Glesner
1988DACA Defect-Tolerant and Fully Testable PLA.Norbert Wehn, Manfred Glesner, K. Caesar, P. Mann, A. Roth
1987DACThe ALGIC Silicon Compiler System: Implementation, Design Experience and Results.Johannes Schuck, Norbert Wehn, Manfred Glesner, G. Kamp