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International Symposium on Design and Diagnostics of Electronic Circuits and Systems

DDECS

C

CORE rank

CORE rank (raw)

C

Fields of research

Computer Systems Engineering

Papers indexed

1,124

2006–2026

Papers per year

200691 peak2026

DDECS papers

1,124 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2008Modeling and observing the jitter in ring oscillators implemented in FPGAs.Boyan Valtchanov, Alain Aubert, Florent Bernard, Viktor Fischer
2008Incremental SAT Instance Generation for SAT-based ATPG.Daniel Tille, Rolf Drechsler
2008Virtual Testing Environment for A/D Converters in Verilog-A and Maple Platform.Ondrej Subrt, Petr Struhovsk, Pravoslav Martnek, Jir Hospodka
2008Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration.Luks Starecek, Luks Sekanina, Zdenek Kotsek
2008A System-On-Chip for Wireless Body Area Sensor Network Node.Zoran Stamenkovic, Goran Panic, Gnter Schoof
2008Controllable Local Clock Signal Generator for Deep Submicron GALS Architectures.Artur L. Sobczyk, Arkadiusz W. Luczyk, Witold A. Pleskacz
2008IP-based Systematic Design of Power-and Matching-limited Circuits.David Smola, Ludk Pantucek
2008Design of Erasure Codes for Digital Multimedia Transmitting.Konstantin V. Shinkarenko, Karel K. Vlcek
2008MPEG-based Performance Comparison between Network-on-Chip and AMBA MPSoC.Rishad A. Shafik, Paul M. Rosinger, Bashir M. Al-Hashimi
2008Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits.Jorge Semio, Juan J. Rodrguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, Joo Paulo Teixeira
2008Low-Voltage Low-Power Highly Linear Down-Sampling Mixer in 65nm Digital CMOS Technology.Kurt Schweiger, Horst Zimmermann
2008Gain reduction by gate-leakage currents in regulated cascodes.Franz Schlgl, Kerstin Schneider-Hornstein, Horst Zimmermann
2008Evaluation of the Iddq Signature in devices with Gauss-distributed background current.Jan Schat
2008Calculating the fault coverage for dual neighboring faults using single stuck-at fault patterns.Jan Schat
2008Implementation of Dynamically Reconfigurable Test Architecture for FPGA Circuits.Martin Rozkovec
2008Mixed-Signal DFT for fully testable ASIC.Frantisek Reznicek
2008Code Coverage Analysis using High-Level Decision Diagrams.Jaan Raik, Uljana Reinsalu, Raimund Ubar, Maksim Jenihhin, Peeter Ellervee
2008Diagnosis of Realistic Defects Based on the X-Fault Model.Ilia Polian, Kohei Miyase, Yusuke Nakamura, Seiji Kajihara, Piet Engelke, Bernd Becker, Stefan Spinner, Xiaoqing Wen
2008Design and Simulation of Runtime Reconfigurable Systems.Thilo Pionteck, Carsten Albrecht, Roman Koch, Torben Brix, Erik Maehle
2008A Dual-Threaded Architecture for Interval Arithmetic Coprocessor with Shared Floating Point Units.Virgil E. Petcu, Alexandru Amaricai, Mircea Vladutiu
2008Software-Based Self-Test Strategy for Data Cache Memories Embedded in SoCs.Wilson J. Prez H., Jaime Velasco-Medina, Danilo Ravotto, Edgar E. Snchez, Matteo Sonza Reorda
2008Mapping of 40 MHz MIMO SDM-OFDM Baseband Processing on Multi-Processor SDR Platform.Martin Palkovic, Hans Cappelle, Miguel Glassee, Bruno Bougard, Liesbet Van der Perre
2008Efficient Allocation of Verification Resources using Revision History Information.Jos Augusto Miranda Nacif, Thiago S. F. Silva, Andra Iabrudi Tavares, Antnio Otvio Fernandes, Claudionor Jos Nunes Coelho Jr.
2008Optimal Backgrounds Selection for Multi Run Memory Testing.Ireneusz Mrozek, Vyacheslav N. Yarmolik
2008Design of Time-to-Digital Converter Output Interface.Marek Miskowicz
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