| 2001 | Computing Phase Noise Eigenfunctions Directly from Harmonic Balance/Shooting Matrices. | Alper Demir, David E. Long, Jaijeet S. Roychowdhury |
| 2001 | Switching Noise Analysis Framework For High Speed Logic Families. | Marco Delaurenti, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni |
| 2001 | Hardware Software Codesign of DSP System Using Grammar Based Approach. | Abhijit K. Deb, Ahmed Hemani, Johnny berg, Adam Postula, Dan Lindqvist |
| 2001 | Satisfying Timing Constraints of Preemptive Real-Time Tasks through Task Layout Technique. | Anupam Datta, Sidharth Choudhury, Anupam Basu, Hiroyuki Tomiyama, Nikil D. Dutt |
| 2001 | Testable Design of Sequential Circuits with Improved Fault Efficiency. | Debesh Kumar Das, Bhargab B. Bhattacharya, Satoshi Ohtake, Hideo Fujiwara |
| 2001 | A Systematic Approach for System Bus Load Reduction Applied to Medical Imaging. | Koen Danckaert, Chidamber Kulkarni, Francky Catthoor, Hugo De Man, Vivek Tiwari |
| 2001 | Software Power Optimizations In An Embedded System. | Vishal Dalal, C. P. Ravikumar |
| 2001 | Efficient Signature-Based Fault Diagnosis Using Variable Size Windows. | Thomas Clouqueur, Ozen Ercevik, Kewal K. Saluja, Hiroshi Takahashi |
| 2001 | Complexity Of Minimum-Delay Gate Resizing. | Supratik Chakraborty, Rajeev Murgai |
| 2001 | Synthesis Of Transparent Circuits For Hierarchical An System-On-A-Chip Test. | Krishnendu Chakrabarty, Andrew Exnicios, Rajatish Mukherjee |
| 2001 | Introduction to SystemC. | Sudipta Bhawmik |
| 2001 | Observability Register Architecture For Efficient Production Test And Debug Of Vlsi Circuits. | Dilip K. Bhavsar, Rishan Tan |
| 2001 | Fd-Tlm Electromagnetic Field Simulation Of High-Speed Iii-V Heterojunction Bipolar Transistor Digital Logic Gates. | Mayukh Bhattacharya, Pinaki Mazumder, Ronald J. Lomax |
| 2001 | Spectral Algorithm To Compute And Synthesize Reduced Order Passive Models For Arbitrary Rc Multiports. | Shabbir H. Batterywala, H. Narayanan |
| 2001 | A Novel Strategy to Test Core Based Designs. | Debabrata Bagchi, Dipanwita Roy Chowdhury, Joy Mukherjee, Santanu Chattopadhyay |
| 2001 | Integrated Crosstalk And Oxide Integrity Analysis In Dsm Designs. | N. V. Arvind, P. R. Suresh, V. Sivakumar, Chandrani Pal, Debaprasad Das |
| 2001 | High Level Synthesis Of Multi-Precision Data Flow Graphs. | Vikas Agrawal, Anand Pande, Mahesh Mehendale |
| 2000 | Estimation of Switching Noise on Power Supply Lines in Deep Sub-micron CMOS Circuits. | Shiyou Zhao, Kaushik Roy |
| 2000 | Verification of a Combinational Loop Based Arbitration Scheme in a System-On-Chip Integration Architecture. | Yang Xia, Pranav Ashar |
| 2000 | A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks. | Yu-Liang Wu, Wangning Long, Hongbing Fan |
| 2000 | Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs. | Liqiong Wei, Kaushik Roy, Vivek De |
| 2000 | Design for Strong Testability of RTL Data Paths to Provide Complete Fault Efficiency. | Hiroki Wada, Toshimitsu Masuzawa, Kewal K. Saluja, Hideo Fujiwara |
| 2000 | Hierarchical Test Generation for Systems On a Chip. | Raghuram S. Tupuri, Jacob A. Abraham, Daniel G. Saab |
| 2000 | Synthesizable RAM-Alternative to Low Configuration Compiler Memory for Die Area Reduction. | B. Suresh, Biswadeep Chaterjee, R. Harinath |
| 2000 | Automatic Validation Test Generation Using Extracted Control Models. | Robert W. Sumners, Jayanta Bhadra, Jacob A. Abraham |