| 2005 | On A Software-Based Self-Test Methodology and Its Application. | Charles H.-P. Wen, Li-C. Wang, Kwang-Ting Cheng, Kai Yang, Wei-Ting Liu, Ji-Jan Chen |
| 2005 | A BIST Scheme for Testing Analog-to-Digital Converters with Digital Response Analyses. | Yun-Che Wen |
| 2005 | SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms. | Baosheng Wang, Yuejian Wu, Josh Yang, Andr Ivanov, Yervant Zorian |
| 2005 | Static Compaction of Delay Tests Considering Power Supply Noise. | Jing Wang, Xiang Lu, Wangqi Qiu, Ziding Yue, Steve Fancler, Weiping Shi, D. M. H. Walker |
| 2005 | A BIST Scheme for FPGA Interconnect Delay Faults. | Chun-Chieh Wang, Jing-Jia Liou, Yen-Lin Peng, Chih-Tsun Huang, Cheng-Wen Wu |
| 2005 | A CMOS RF RMS Detector for Built-in Testing of Wireless Transceivers. | Alberto Valdes-Garcia, Radhika Venkatasubramanian, Rangakrishnan Srinivasan, Jos Silva-Martnez, Edgar Snchez-Sinencio |
| 2005 | Defect Screening Using Independent Component Analysis on I_DDQ. | Ritesh P. Turakhia, Brady Benware, Robert Madge, Thaddeus T. Shannon, W. Robert Daasch |
| 2005 | Defect Tolerance for Gracefully-Degradable Microfluidics-Based Biochips. | Fei Su, Krishnendu Chakrabarty |
| 2005 | Constructive Derivation of Analog Specification Test Criteria. | Haralampos-G. D. Stratigopoulos, Yiorgos Makris |
| 2005 | Synthesis of X-Tolerant Convolutional Compactors. | Janusz Rajski, Jerzy Tyszer |
| 2005 | Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies. | Ilia Polian, Sandip Kundu, Jean-Marc Gallire, Piet Engelke, Michel Renovell, Bernd Becker |
| 2005 | Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays. | Gustavo Pereira, Antonio Andrade Jr., Tiago R. Balen, Marcelo Lubaszewski, Florence Azas, Michel Renovell |
| 2005 | Effective TARO Pattern Generation. | Intaik Park, Ahmad A. Al-Yamani, Edward J. McCluskey |
| 2005 | Low Cost Scheme for On-Line Clock Skew Compensation. | Martin Omaa, Daniele Rossi, Cecilia Metra |
| 2005 | Pattern Generation and Estimation for Power Supply Noise Analysis. | Mehrdad Nourani, Mohammad Tehranipoor, Nisar Ahmed |
| 2005 | Closed-Form Simulation and Robustness Models for SEU-Tolerant Design. | Kartik Mohanram |
| 2005 | Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking. | Chunsheng Liu, Vikram Iyengar, Jiangfan Shi, rika F. Cota |
| 2005 | Pseudo-Functional Scan-based BIST for Delay Fault. | Yung-Chieh Lin, Feng Lu, Kwang-Ting Cheng |
| 2005 | Unsatisfiability Based Efficient Design for Testability Solution for Register-Transfer Level Circuits. | Loganathan Lingappan, Niraj K. Jha |
| 2005 | An Economic Selecting Model for DFT Strategies. | Yu-Ting Lin, Tony Ambler |
| 2005 | Modeling and Testing Comparison Faults for Ternary Content Addressable Memories. | Jin-Fu Li, Chou-Kun Lin |
| 2005 | On Silicon-Based Speed Path Identification. | Leonard Lee, Li-C. Wang, Praveen Parvathala, T. M. Mak |
| 2005 | Reducing Pattern Delay Variations for Screening Frequency Dependent Defects. | Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir |
| 2005 | Test and Characterization of a Variable-Capacity Multilevel DRAM. | John C. Koob, Sue Ann Ung, Ashwin S. Rao, Daniel A. Leder, Craig S. Joly, Kristopher C. Breen, Tyler L. Brandon, Michael Hume, Bruce F. Cockburn, Duncan G. Elliott |
| 2005 | Reduction of Instantaneous Power by Ripple Scan Clocking. | Kirti Joshi, Eric W. MacDonald |