| 2025 | DAC | Machine Learning-Driven STL Generation for Enhancing Functional Safety of E/E Systems. | Sanjay Das, Swastik Bhattacharya, Anand Menon, Shamik Kundu, Pooja Madhusoodhanan, Prasanth Viswanathan Pillai, Rubin A. Parekhji, Arnab Raha, Suvadeep Banerjee, Suriyaprakash Natarajan, Kanad Basu |
| 2025 | ITC | NeuralTPG: GPU-Accelerated Neural Twin-Based Test Pattern Generation for Transition Delay Faults in Safety-Critical Applications. | Xuanyi Tan, Gitanjali Mukherjee, Dhruv Thapar, Arjun Chaudhuri, Sanmitra Banerjee, Rubin A. Parekhji, Krishnendu Chakrabarty |
| 2025 | VTS | Defect Severity Analysis for Analog Circuits Using Zoom Search and Hierarchical Fault Simulation. | Mehmet Onder, Lakshmanan Balasubramanian, Rubin A. Parekhji, Suriyaprakash Natarajan, Sule Ozev |
| 2024 | DAC | Graph Learning-based Fault Criticality Analysis for Enhancing Functional Safety of E/E Systems. | Sanjay Das, Shamik Kundu, Pooja Madhusoodhanan, Viswanathan Pillai Prasanth, Rubin A. Parekhji, Arnab Raha, Suvadeep Banerjee, Suriya Natarajan, Kanad Basu |
| 2024 | ETS | Hierarchical Fault Simulation for Mixed-Signal Circuits Using Template Based Fault Response Modeling. | Tolga Aksoy, Nikhil Sagar Modala, Lakshmanan Balasubramanian, Rubin A. Parekhji, Sule Ozev |
| 2024 | ITC | Safety-Guided Test Generation for Structural Faults. | Xuanyi Tan, Dhruv Thapar, Deepesh Sahoo, Arjun Chaudhuri, Sanmitra Banerjee, Krishnendu Chakrabarty, Rubin A. Parekhji |
| 2022 | VTS | Innovative Practices Track: New Methods for System Level Test of Image Projection and Radar VLSI Systems. | Rubin A. Parekhji |
| 2021 | ITC | Exploiting Application Tolerance for Functional Safety. | V. Prasanth, Rubin A. Parekhji, Bharadwaj Amrutur |
| 2019 | VLSID | Perturbation Based Workload Augmentation for Comprehensive Functional Safety Analysis. | V. Prasanth, Rubin A. Parekhji, Bharadwaj Amrutur |
| 2018 | VLSID | Towards Single Pin Scan for Extremely Low Pin Count Test. | Mudasir S. Kawoosa, Rajesh K. Mittal, Maheedhar Jalasuthram, Rubin A. Parekhji |
| 2017 | ITC | Low cost dynamic error detection in linearity testing of SAR ADCs. | Nimit Jain, Nitin Agarwal, Rajavelu Thinakaran, Rubin A. Parekhji |
| 2017 | ITC | Safety analysis for integrated circuits in the context of hybrid systems. | V. Prasanth, Rubin A. Parekhji, Bharadwaj Amrutur |
| 2017 | VTS | Innovative practices session 2C: "How is industry simplifying analog test". | Rubin A. Parekhji, Srinivas Modekurty |
| 2017 | VTS | An optimised SDD ATPG and SDQL computation method across different pattern sets. | Wilson Pradeep, Prakash Narayanan, Rubin A. Parekhji |
| 2016 | VTS | A novel technique for interdependent trim code optimization. | Pankaj Bongale, Vinothkumar Sundaresan, Partha Ghosh, Rubin A. Parekhji |
| 2015 | DATE | On-chip measurement of bandgap reference voltage using a small form factor VCO based zoom-in ADC. | Osman Emir Erol, Sule Ozev, Chandra K. H. Suresh, Rubin A. Parekhji, Lakshmanan Balasubramanian |
| 2015 | VLSID | New Methods for Simulation Speed-up and Test Qualification with Analog Fault Simulation. | V. R. Devanathan, Lakshmanan Balasubramanian, Rubin A. Parekhji |
| 2014 | DATE | Multi-site test optimization for multi-Vdd SoCs using space- and time- division multiplexing. | Fotis Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Rubin A. Parekhji, Arvind Jain |
| 2014 | ITC | Systematic approach for trim test time optimization: Case study on a multi-core RF SOC. | Rajesh Mittal, Mudasir Kawoosa, Rubin A. Parekhji |
| 2013 | DATE | Towards adaptive test of multi-core RF SoCs. | Rajesh Mittal, Lakshmanan Balasubramanian, Y. B. Chethan Kumar, V. R. Devanathan, Mudasir Kawoosa, Rubin A. Parekhji |
| 2012 | ETS | Time-division multiplexing for testing SoCs with DVS and multiple voltage islands. | Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji |
| 2012 | VTS | Derating based hardware optimizations in soft error tolerant designs. | V. Prasanth, Virendra Singh, Rubin A. Parekhji |
| 2011 | IOLTS | Reduced overhead soft error mitigation using error control coding techniques. | V. Prasanth, Virendra Singh, Rubin A. Parekhji |
| 2011 | ITC | DFT for extremely low cost test of mixed signal SOCs with integrated RF and power management. | Rajesh Mittal, Lakshmanan Balasubramanian, Adesh Sontakke, Harikrishna Parthasarathy, Prakash Narayanan, Puneet Sabbarwal, Rubin A. Parekhji |
| 2011 | VLSID | Multi-CoDec Configurations for Low Power and High Quality Scan Test. | Arvind Jain, Sundarrajan Subramanian, Rubin A. Parekhji, Srivaths Ravi |
| 2011 | VTS | An efficient test data reduction technique through dynamic pattern mixing across multiple fault models. | Srinivasulu Alampally, R. T. Venkatesh, Priyadharshini Shanmugasundaram, Rubin A. Parekhji, Vishwani D. Agrawal |
| 2010 | IOLTS | Robust detection of soft errors using delayed capture methodology. | V. Prasanth, Virendra Singh, Rubin A. Parekhji |
| 2010 | VTS | Test time reduction using parallel RF test techniques. | Rajesh Mittal, Adesh Sontakke, Rubin A. Parekhji |
| 2010 | VTS | Innovative practices session 1C: Innovative practices in RF test. | Rubin A. Parekhji |
| 2010 | VTS | A generic low power scan chain wrapper for designs using scan compression. | Amit Sabne, Rajesh Tiwari, Abhijeet Shrivastava, Srivaths Ravi, Rubin A. Parekhji |
| 2009 | IOLTS | Design techniques and tradeoffs in implementing non-destructive field test using logic BIST self-test. | Amit Dutta, Malav Shah, G. Swathi, Rubin A. Parekhji |
| 2008 | IOLTS | False Error Study of On-line Soft Error Detection Mechanisms. | M. Kiran Kumar Reddy, Bharadwaj S. Amrutur, Rubin A. Parekhji |
| 2008 | ITC | DFT Implementationis for Striking the Right Balance between Test Cost and Test Quality for Automotive SOCs. | Amit Dutta, Srinivasulu Alampally, V. Prasanth, Rubin A. Parekhji |
| 2008 | VTS | A Regression Based Technique for ATE-Aware Test Data Volume Estimation of System-on-Chips. | Rajesh Tiwari, Abhijeet Shrivastava, Mahit Warhadpande, Srivaths Ravi, Rubin A. Parekhji |
| 2007 | ICCAD | Methodology for low power test pattern generation using activity threshold control logic. | Srivaths Ravi, V. R. Devanathan, Rubin A. Parekhji |
| 2007 | VLSID | Enhancements in Deterministic BIST Implementations for Improving Test of Complex SOCs. | Sandeep Jain, Jais Abraham, Srinivas Kumar Vooka, Sumant Kale, Amit Dutta, Rubin A. Parekhji |
| 2007 | VLSID | Modeling Techniques for Formal Verification of BIST Controllers and Their Integration into SOC Designs. | Subir K. Roy, Rubin A. Parekhji |
| 2007 | VLSID | Modified Stability Checking for On-line Error Detection. | Satish Yada, Bharadwaj S. Amrutur, Rubin A. Parekhji |
| 2006 | ITC | On-chip Test and Repair of Memories for Static and Dynamic Faults. | Sanjay K. Thakur, Rubin A. Parekhji, Arun N. Chandorkar |
| 2006 | VTS | Session Abstract. | Rubin A. Parekhji |
| 2004 | ITC | DFT for Test Optimisations in a Complex Mixed-Signal SOC - Case Study on TI's TNETD7300 ADSL Modem Device. | K. Nikila, Rubin A. Parekhji |
| 2004 | VLSID | Built-in Self-test Technique for Selective Detection of Neighbourhood Pattern Sensitive Faults in Memories. | Rajeshwar S. Sable, Ravindra P. Saraf, Rubin A. Parekhji, Arun N. Chandorkar |
| 2003 | ITC | Panel Synopsis - How (In)Adequate is One Time Testing? | Rubin A. Parekhji |
| 2003 | VLSID | Testing Embedded Cores and SOCs-DFT, ATPG and BIST Solutions. | Rubin A. Parekhji |
| 2002 | VLSID | Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon. | Karanth Shankaranarayana, Soujanna Sarkar, R. Venkatraman, Shyam S. Jagini, N. Venkatesh, Jagdish C. Rao, H. Udayakumar, M. Sambandam, K. P. Sheshadri, S. Talapatra, Parag Mhatre, Jais Abraham, Rubin A. Parekhji |
| 2000 | ITC | A framework to evaluate test tradeoffs in embedded core based systems-case study on TI's TMS320C27xx. | Jais Abraham, Narayan Prasad, Srinivasa Chakravarthy B. S., Ameet Bagwe, Rubin A. Parekhji |
| 2000 | VLSID | Test Techniques and Trade-offs for Embedded Cores and Systems. | Rubin A. Parekhji |
| 1995 | VLSID | A new methodology for the design of low-cost fail safe circuits and networks. | B. Ravi Kishore, Rubin A. Parekhji, Sandeep Pagey, Sunil D. Sherlekar, G. Venkatesh |
| 1993 | VLSID | State Assignment for Optimal Design of Monitored Self-Checking Sequential Circuits. | Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar |
| 1991 | ITC | A Methodology for Designing Optimal Self-Checking Sequential Circuits. | Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar |
| 1989 | MICRO | Design methodology and microdiagnostics development for a self-checking microprocessor. | Rubin A. Parekhji, N. K. Nanda |