| 2023 | DSN | YODA: Covert Communication Channel over Public DNS Resolvers. | Sandip Saha, Sareena Karapoola, Chester Rebeiro, V. Kamakoti |
| 2022 | CIKM | RaDaR: A Real-Word Dataset for AI powered Run-time Detection of Cyber-Attacks. | Sareena Karapoola, Nikhilesh Singh, Chester Rebeiro, V. Kamakoti |
| 2019 | ICCAD | Karna: A Gate-Sizing based Security Aware EDA Flow for Improved Power Side-Channel Attack Protection. | Patanjali SLPSK, Prasanna Karthik Vairam, Chester Rebeiro, V. Kamakoti |
| 2016 | ISLPED | STOCK: Stochastic Checkers for Low-overhead Approximate Error Detection. | Neel Gala, Swagath Venkataramani, Anand Raghunathan, V. Kamakoti |
| 2016 | VLSID | ChADD: An ADD Based Chisel Compiler with Reduced Syntactic Variance. | Vikas Chauhan, Neel Gala, V. Kamakoti |
| 2016 | VLSID | SHAKTI Processors: An Open-Source Hardware Initiative. | Neel Gala, Arjun Menon, Rahul Bodduna, G. S. Madhusudan, V. Kamakoti |
| 2015 | DATE | DP-fill: a dynamic programming approach to X-filling for minimizing peak test power in scan tests. | Satya Trinadh, Ch. Sobhan Babu, Shiv Govind Singh, Seetal Potluri, V. Kamakoti |
| 2015 | VLSID | Framework for Selective Flip-Flop Replacement for Soft Error Mitigation. | Pavan Vithal Torvi, V. R. Devanathan, V. Kamakoti |
| 2014 | VLSID | ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICs. | Neel Gala, V. R. Devanathan, Karthik Srinivasan, V. Visvanathan, V. Kamakoti |
| 2013 | ETS | PinPoint: An algorithm for enhancing diagnostic resolution using capture cycle power information. | Seetal Potluri, Satya Trinadh, Roopashree Baskaran, Nitin Chandrachoodan, V. Kamakoti |
| 2010 | VLSID | Impact of Temperature on Test Quality. | Lavanya Jagan, Camelia Hora, Bram Kruseman, Stefan Eichenberger, Ananta K. Majhi, V. Kamakoti |
| 2009 | VLSID | Efficient Grouping of Fail Chips for Volume Yield Diagnostics. | Lavanya Jagan, Ratan Deep Singh, V. Kamakoti, Ananta K. Majhi |
| 2007 | DATE | Interactive presentation: On power-profiling and pattern generation for power-safe scan tests. | V. R. Devanathan, C. P. Ravikumar, V. Kamakoti |
| 2007 | ITC | A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test. | V. R. Devanathan, C. P. Ravikumar, V. Kamakoti |
| 2007 | ITC | PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test. | V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti |
| 2007 | VLSID | Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms. | V. R. Devanathan, C. P. Ravikumar, V. Kamakoti |
| 2007 | VLSID | Controllability-driven Power Virus Generation for Digital Circuits. | K. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekananda M. Vedula |
| 2007 | VTS | Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test. | V. R. Devanathan, C. P. Ravikumar, V. Kamakoti |
| 2007 | VTS | Power Virus Generation Using Behavioral Models of Circuits. | K. Najeeb, Vishnu Vardhan Reddy Konda, Siva Kumar Sastry Hari, V. Kamakoti, Vivekananda M. Vedula |
| 2006 | VLSID | An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs. | Vivek Garg, Vikram Chandrasekhar, Milagros Sashiknth, V. Kamakoti |
| 2006 | VLSID | Ultra Folded High-Speed Architectures for Reed-Solomon Decoders. | Kavish Seth, K. N. Viswajith, S. Srinivasan, V. Kamakoti |
| 2005 | ASPDAC | A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs. | Vivek Garg, Vikram Chandrasekhar, Milagros Sashiknth, V. Kamakoti |
| 2005 | ASPDAC | A function generator-based reconfigurable system. | Vivek Garg, Vikram Chandrasekhar, Milagros Sashiknth, V. Kamakoti |
| 2005 | ASPDAC | Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs. | E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashiknth, V. Kamakoti, Narayanan Vijaykrishnan |
| 2005 | DATE | FPGA based Agile Algorithm-On-Demand Co-Processor. | Ramachandran Pradeep, S. Vinay, Sanjay Burman, V. Kamakoti |
| 2005 | FPGA | Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only). | E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashiknth, V. Kamakoti, Narayanan Vijaykrishnan |
| 2005 | VLSID | A Universal Random Test Generator for Functional Verification of Microprocessors and System-on-Chip. | K. Uday Bhaskar, M. Prasanth, G. Chandramouli, V. Kamakoti |
| 2005 | VLSID | Placement and Routing for 3D-FPGAs Using Reinforcement Learning and Support Vector Machines. | R. Manimegalai, E. Siva Soumya, Vaishnavi Muralidharan, Balaraman Ravindran, V. Kamakoti, Dinesh Bhatia |
| 2005 | VLSID | A Principal Component Neural Network-Based Face Recognition System and Its ASIC Implementation. | Chakka Siva Sai Prasanna, N. Sudha, V. Kamakoti |
| 2005 | VLSID | Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs. | E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashiknth, V. Kamakoti, Narayanan Vijaykrishnan |
| 2004 | DATE | MemMap: Technology Mapping Algorithm for Area Reduction in FPGAs with Embedded Memory Arrays Using Reconvergence Analysis. | A. Manoj Kumar, Jayaram Bobba, V. Kamakoti |
| 2004 | FPGA | SHAPER: synthesis for hybrid FPGA architectures containing PLA elements using reconvergence analysis. | A. Manoj Kumar, B. Jayaram, V. Kamakoti |
| 2004 | FPL | MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Blocks. | R. Manimegalai, A. Manoj Kumar, B. Jayaram, V. Kamakoti |
| 2004 | ICONIP | Face Recognition Using Weighted Modular Principle Component Analysis. | A. Pavan Kumar, Sukhendu Das, V. Kamakoti |
| 2004 | ICONIP | A Hardware-Directed Face Recognition System Based on Local Eigen-analysis with PCNN. | Chakka Siva Sai Prasanna, N. Sudha, V. Kamakoti |
| 2004 | VLSID | A Parallel Architectural Implementation Of The New Three-Step Search Algorithm For Block Motion Estimation. | Kavish Seth, P. Rangarajan, S. Srinivasan, V. Kamakoti, V. Bala Kuteshwar |
| 2004 | VLSID | A Bus Encoding Technique for Power and Cross-talk Minimization. | P. Subrahmanya, R. Manimegalai, V. Kamakoti, Madhu Mutyam |
| 2003 | CEC | An enhanced evolutionary approach to spatial partitioning for reconfigurable environments. | Permandla Pratibha, Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti |
| 2003 | FPL | Testable Clock Routing Architecture for Field Programmable Gate Arrays. | L. Kalyan Kumar, Amol J. Mupid, Aditya S. Ramani, V. Kamakoti |
| 2003 | HiPC | Parallel Partitioning Techniques for Logic Minimization Using Redundancy Identification. | B. Jayaram, A. Manoj Kumar, V. Kamakoti |
| 2001 | INDOCRYPT | Toward Optimal Player Weights in Secure Distributed Protocols. | K. Srinathan, C. Pandu Rangan, V. Kamakoti |
| 1998 | COCOON | The Colored Sector Search Tree: A Dynamic Data Structure for Efficient High Dimensional Nearest-Foreign-Neighbor Queries. | Thomas Graf, V. Kamakoti, N. S. Janaki Latha, C. Pandu Rangan |
| 1997 | HiPC | An optimal parallel algorithm for the all-nearest-foreign-neighbors problem in arbitrary dimensions. | Thomas Graf, V. Kamakoti, N. S. Janaki Latha, C. Pandu Rangan |
| 1997 | ICPADS | Efficient Algorithms for Prefix and General Prefix Computations on Distributed Shared Memory Systems with Applications. | V. Kamakoti, N. Balakrishnan |
| 1995 | COCOON | Efficient Randomized Incremental Algorithm For The Closest Pair Problem Using Leafary Trees. | V. Kamakoti, Kamala Krithivasan, C. Pandu Rangan |