| 2022 | SDM | A Strong Node Classification Baseline for Temporal Graphs. | Farimah Poursafaei, Zeljko Zilic, Reihaneh Rabbany |
| 2021 | PAKDD | SigTran: Signature Vectors for Detecting Illicit Activities in Blockchain Transaction Networks. | Farimah Poursafaei, Reihaneh Rabbany, Zeljko Zilic |
| 2019 | ICIP | A Structurally Regularized Convolutional Neural Network for Image Classification Using Wavelet-Based Subband Decomposition. | Pavel Sinha, Ioannis N. Psaromiligkos, Zeljko Zilic |
| 2019 | MVA | Exploring Better Food Detection via Transfer Learning. | Jianing Sun, Katarzyna Radecka, Zeljko Zilic |
| 2018 | BIBE | Software Defined Radio-Based Testbed for Wireless Body Area Network. | Zhiyu Chen, Junchao Wang, Kaining Han, Zeljko Zilic |
| 2018 | ISCAS | A Continuous Respiratory Monitoring System Using Ultrasound Piezo Transducer. | Amirhossein Shahshahani, Sharmistha Bhadra, Zeljko Zilic |
| 2018 | ISCAS | An ASIC Implementation of Security Scheme for Body Area Networks. | Junchao Wang, Kaining Han, Anastasios Alexandridis, Zeljko Zilic, Yu Pang, Jinzhao Lin |
| 2017 | BSN | Evaluation of an RF wearable device for non-invasive real-time hydration monitoring. | Junchao Wang, Zeljko Zilic, Yutian Shu |
| 2017 | ICIN | Concealed regression for aggregation in low power wireless networks. | Andrey Tolstikhin, Zeljko Zilic |
| 2017 | ISCAS | Ultrasound sensors and its application in human heart rate monitoring. | Amirhossein Shahshahani, Davood Raeisi Nafchi, Zeljko Zilic |
| 2016 | FNC | Mobility and Direction Aware Ad-hoc on Demand Distance Vector Routing Protocol. | Andraws I. Swidan, Haytham Bani Abdelghany, Ramzi R. Saifan, Zeljko Zilic |
| 2016 | BSN | ECG compression for mobile sensor platforms. | Yi Steven Ding, Zeljko Zilic |
| 2015 | BSN | FLogFS: A lightweight flash log file system. | Benjamin Nahill, Zeljko Zilic |
| 2014 | BIBE | Design of an e-Health Respiration and Body Posture Monitoring System and Its Application for Rib Cage and Abdomen Synchrony Analysis. | Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic |
| 2013 | CASES | Tutorial: Methodologies and tools for embedded multisensory systems based on ARM cortex M processors. | Zeljko Zilic |
| 2013 | ETFA | An FPGA implementation of wait-free data synchronization protocols. | Benjamin Nahill, Ari Ramdial, Haibo Zeng, Marco Di Natale, Zeljko Zilic |
| 2013 | BSN | An efficient fault-tolerant sensor fusion algorithm for accelerometers. | Omid Sarbishei, Benjamin Nahill, Atena Roshan Fekr, Majid Janidarmian, Katarzyna Radecka, Zeljko Zilic, Boris Karajica |
| 2012 | ICCD | MSE minimization and fault-tolerant data fusion for multi-sensor systems. | Atena Roshan Fekr, Majid Janidarmian, Omid Sarbishei, Benjamin Nahill, Katarzyna Radecka, Zeljko Zilic |
| 2011 | ASPDAC | An efficient hybrid engine to perform range analysis and allocate integer bit-widths for arithmetic circuits. | Yu Pang, Katarzyna Radecka, Zeljko Zilic |
| 2011 | DSD | On Failure Rate Assessment Using an Executable Model of the System. | Mohammad Hossein Neishaburi, Zeljko Zilic |
| 2011 | VTS | A distributed AXI-based platform for post-silicon validation. | Mohammad Hossein Neishaburi, Zeljko Zilic |
| 2010 | DATE | Enabling efficient post-silicon debug by clustering of hardware-assertions. | Mohammad Hossein Neishaburi, Zeljko Zilic |
| 2009 | DAC | Serial reconfigurable mismatch-tolerant clock distribution. | Atanu Chattopadhyay, Zeljko Zilic |
| 2008 | DATE | Built-in Clock Skew System for On-line Debug and Repair. | Atanu Chattopadhyay, Zeljko Zilic |
| 2007 | ASPDAC | Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation. | Marc Boule, Zeljko Zilic |
| 2007 | DAC | Modeling Simultaneous Switching Noise-Induced Jitter for System-on-Chip Phase-Locked Loops. | Henry H. Y. Chan, Zeljko Zilic |
| 2007 | DATE | Reversible circuit technology mapping from non-reversible specifications. | Zeljko Zilic, Katarzyna Radecka, Ali Kazamiphur |
| 2007 | ISCAS | A Performance Driven Layout Compaction Optimization Algorithm for Analog Circuits. | Henry H. Y. Chan, Zeljko Zilic |
| 2007 | ISCAS | Reconfigurable Clock Distribution Circuitry. | Atanu Chattopadhyay, Zeljko Zilic |
| 2007 | ITC | A high accuracy high throughput jitter test solution on ATE for 3GBPS and 6gbps serial-ata. | Yongquan Fan, Yi Cai, Zeljko Zilic |
| 2006 | ICCD | Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug. | Marc Boule, Jean-Samuel Chenard, Zeljko Zilic |
| 2006 | ITC | An Accelerated Jitter Tolerance Test Technique on Ate for 1.5GB/S and 3GB/S Serial-ATA. | Yongquan Fan, Yi Cai, Liming Fang, Anant Verma, William Burchanowski, Zeljko Zilic, Sandeep Kumar |
| 2006 | VTS | Energy Efficient Software-Based Self-Test for Wireless Sensor Network Nodes. | Rong Zhang, Zeljko Zilic, Katarzyna Radecka |
| 2005 | DAC | Design methodology for wireless nodes with printed antennas. | Jean-Samuel Chenard, Chun Yiu Chu, Zeljko Zilic, Milica Popovic |
| 2005 | ICCD | Incorporating Ef.cient Assertion Checkers into Hardware Emulation. | Marc Boule, Zeljko Zilic |
| 2004 | ICCD | FPGA Emulation of Quantum Circuits. | Ahmed Usman Khalid, Zeljko Zilic, Katarzyna Radecka |
| 2004 | ISCAS | A novel scheme of implementing high speed AWGN communication channel emulators in FPGAs. | Yongquan Fan, Zeljko Zilic |
| 2004 | ITC | Architectures of Increased Availability Wireless Sensor Network Nodes. | Man Wah Chiang, Zeljko Zilic, Jean-Samuel Chenard, Katarzyna Radecka |
| 2003 | FPGA | Testing for bit error rate in FPGA communication interfaces. | Yongquan Fan, Zeljko Zilic |
| 2003 | VTS | Layered Approach to Designing System Test Interfaces. | Man Wah Chiang, Zeljko Zilic |
| 2002 | FPGA | FPGA test time reduction through a novel interconnect testing scheme. | Stuart McCracken, Zeljko Zilic |
| 2002 | ICCAD | Specifying and verifying imprecise sequential datapaths by Arithmetic Transforms. | Katarzyna Radecka, Zeljko Zilic |
| 2002 | VLSID | Identifying Redundant Wire Replacements for Synthesis and Verification. | Katarzyna Radecka, Zeljko Zilic |
| 2001 | ICCD | Arithmetic Transforms for Verifying Compositions of Sequential Datapaths. | Katarzyna Radecka, Zeljko Zilic |
| 2001 | ISCAS | A new PLL design for clock management applications. | Ian Brynjolfson, Zeljko Zilic |
| 2001 | ITC | : Identifying redundant gate replacements in verification by error modeling. | Zeljko Zilic, Katarzyna Radecka |
| 2000 | FPGA | FPGA clock management for low power applications (poster abstract). | Ian Brynjolfson, Zeljko Zilic |
| 2000 | ICPP | The NUMAchine Multiprocessor. | R. Grindley, Tarek S. Abdelrahman, Stephen Brown, S. Caranci, D. DeVries, Benjamin Gamsa, A. Grbic, M. Gusat, R. Ho, Orran Krieger, Guy G. Lemieux, K. Loveless, Naraig Manjikian, P. McHardy, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic |
| 2000 | VTS | Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling. | Katarzyna Radecka, Zeljko Zilic |
| 1999 | ISSAC | On Feasible Multivariate Polynomial Interpolations over Arbitrary Fields. | Zeljko Zilic, Katarzyna Radecka |
| 1998 | DAC | Design and Implementation of the NUMAchine Multiprocessor. | A. Grbic, Stephen Brown, S. Caranci, R. Grindley, M. Gusat, Guy G. Lemieux, K. Loveless, Naraig Manjikian, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic |
| 1996 | DAC | Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools. | Stephen Brown, Naraig Manjikian, Zvonko G. Vranesic, S. Caranci, A. Grbic, R. Grindley, M. Gusat, K. Loveless, Zeljko Zilic, Sinisa Srbljic |
| 1996 | FPGA | Using BDDs to Design ULMs for FPGAs. | Zeljko Zilic, Zvonko G. Vranesic |