| 2026 | ASPDAC | Chiplet-NAS: Chiplet-aware Neural Architecture Search for Efficient AI Inference on 2.5D Integration. | Cheng Guo, Pragnya Sudershan Nalla, Nikhil K. Cherukuri, Rui Xue, Sachin S. Sapatnekar, Chaitali Chakrabarti, Yu Cao, Jeff Zhang |
| 2026 | ASPDAC | Accelerating Electrostatics-based Global Placement with Enhanced FFT Computation. | Hangyu Zhang, Sachin S. Sapatnekar |
| 2026 | FCCM | A Hybrid Ising FPGA-COBI Architecture with Hardware-Based Problem Decomposition. | Ruihong Yin, Yue Zheng, Chaohui Li, Ahmet Efe, Abhimanyu Kumar, Ziqing Zeng, Ulya R. Karpuzcu, Sachin S. Sapatnekar, Chris H. Kim |
| 2026 | ISCA | SATIC: An Optimizing Ising Compiler for SAT(isfiability). | Ahmet Efe, Hsrev Cilasun, Abhimanyu Kumar, Nafisa Sadaf Prova, Ziqing Zeng, Tahmida Islam, Ruihong Yin, Chaohui Li, Peter Kreye, Chris H. Kim, Sachin S. Sapatnekar, Ulya R. Karpuzcu |
| 2025 | DAC | Invited: EDA for Heterogeneous Integration. | Emad Haque, Pragnya Sudershan Nalla, Chetal Choppali Sudarshan, Divya Yogi, Hangyu Zhang, Chaitali Chakrabarti, Vidya A. Chhabria, Ramesh Harjani, Jeff Zhang, Sachin S. Sapatnekar |
| 2025 | DATE | Accelerating OTA Circuit Design: Transistor Sizing Based on a Transformer Model and Precomputed Lookup Tables. | Subhadip Ghosh, Endalk Y. Gebru, Chandramouli V. Kashyap, Ramesh Harjani, Sachin S. Sapatnekar |
| 2025 | DATE | ML-Based AIG Timing Prediction to Enhance Logic Optimization. | Wenjing Jiang, Jin Yan, Sachin S. Sapatnekar |
| 2025 | DATE | CLAIRE: Composable Chiplet Libraries for AI Inference. | Pragnya Sudershan Nalla, Emad Haque, Yaotian Liu, Sachin S. Sapatnekar, Jeff Zhang, Chaitali Chakrabarti, Yu Cao |
| 2025 | ICCAD | Optimal Selection and Placement of Voltage Regulators in 2.5D Heterogeneously Integrated Systems. | Hangyu Zhang, Divya Yogi, Ramesh Harjani, Sachin S. Sapatnekar |
| 2024 | ASPDAC | Reinforcing the Connection between Analog Design and EDA (Invited Paper). | Kishor Kunal, Meghna Madhusudan, Jitesh Poojary, S. Ramprasath, Arvind K. Sharma, Ramesh Harjani, Sachin S. Sapatnekar |
| 2024 | ASPDAC | Automated synthesis of mixed-signal ML inference hardware under accuracy constraints. | Kishor Kunal, Jitesh Poojary, S. Ramprasath, Ramesh Harjani, Sachin S. Sapatnekar |
| 2024 | DATE | On Gate Flip Errors in Computing-In-Memory. | Zamshed I. Chowdhury, Hsrev Cilasun, Salonik Resch, Masoud Zabihi, Yang Lv, Brandon Zink, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu |
| 2024 | HPCA | ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based Architectures for Sustainable VLSI. | Chetan Choppali Sudarshan, Nikhil Matkar, Sarma B. K. Vrudhula, Sachin S. Sapatnekar, Vidya A. Chhabria |
| 2024 | ICCAD | Generative Methods in EDA: Innovations in Dataset Generation and EDA Tool Assistants. | Vidya A. Chhabria, Bing-Yue Wu, Utsav Sharma, Kishor Kunal, Austin Rovinski, Sachin S. Sapatnekar |
| 2024 | ICCAD | Analyzing the Impact of FinFET Self-Heating on the Performance of RF Power Amplifiers. | Nibedita Karmokar, Sai-Wang Tam, Thanh Viet Dinh, Vidya A. Chhabria, Ramesh Harjani, Sachin S. Sapatnekar |
| 2024 | ISCA | On Error Correction for Nonvolatile Processing-In-Memory. | Hsrev Cilasun, Salonik Resch, Zamshed I. Chowdhury, Masoud Zabihi, Yang Lv, Brandon Zink, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu |
| 2024 | ISLPED | Hardware Acceleration of Inference on Dynamic GNNs. | Sudipta Mondal, Sachin S. Sapatnekar |
| 2024 | VTS | OpenROAD and CircuitOps: Infrastructure for ML EDA Research and Education. | Vidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng, Rongjian Liang, Haoxing Ren, Sachin S. Sapatnekar, Bing-Yue Wu |
| 2023 | ASPDAC | Reusing GEMM Hardware for Efficient Execution of Depthwise Separable Convolution on ASIC-Based DNN Accelerators. | Susmita Dey Manasi, Suvadeep Banerjee, Abhijit Davare, Anton A. Sorokin, Steven M. Burns, Desmond A. Kirkpatrick, Sachin S. Sapatnekar |
| 2023 | DATE | AuxcellGen: A Framework for Autonomous Generation of Analog and Memory Unit Cells. | Sumanth Kamineni, Arvind K. Sharma, Ramesh Harjani, Sachin S. Sapatnekar, Benton H. Calhoun |
| 2023 | DATE | Minimum Unit Capacitance Calculation for Binary-Weighted Capacitor Arrays. | Nibedita Karmokar, Ramesh Harjani, Sachin S. Sapatnekar |
| 2023 | DATE | Energy-efficient Hardware Acceleration of Shallow Machine Learning Applications. | Ziqing Zeng, Sachin S. Sapatnekar |
| 2023 | ICCAD | Frequency-Domain Transient Electromigration Analysis Using Circuit Theory. | Mohammad Abdullah Al Shohel, Vidya A. Chhabria, Nestoras E. Evmorfopoulos, Sachin S. Sapatnekar |
| 2023 | ISCA | On Endurance of Processing in (Nonvolatile) Memory. | Salonik Resch, M. Hsrev Cilasun, Zamshed I. Chowdhury, Masoud Zabihi, Zhengyang Zhao, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu |
| 2023 | ISLPED | A Multicore GNN Training Accelerator. | Sudipta Mondal, Ramprasath S, Ziqing Zeng, Kishor Kunal, Sachin S. Sapatnekar |
| 2022 | ASPDAC | Common-Centroid Layout for Active and Passive Devices: A Review and the Road Ahead. | Nibedita Karmokar, Meghna Madhusudan, Arvind K. Sharma, Ramesh Harjani, Mark Po-Hung Lin, Sachin S. Sapatnekar |
| 2022 | DAC | GNNIE: GNN inference engine with load-balancing and graph-specific caching. | Sudipta Mondal, Susmita Dey Manasi, Kishor Kunal, Ramprasath S, Sachin S. Sapatnekar |
| 2022 | DATE | A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement. | Tonmoy Dhar, Ramprasath S, Jitesh Poojary, Soner Yaldiz, Steven M. Burns, Ramesh Harjani, Sachin S. Sapatnekar |
| 2022 | DATE | Constructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor Arrays. | Nibedita Karmokar, Arvind K. Sharma, Jitesh Poojary, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar |
| 2022 | DATE | Are Analytical Techniques Worthwhile for Analog IC Placement? | Yishuang Lin, Yaguang Li, Donghao Fang, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu |
| 2022 | ICCAD | A Novel Semi-Analytical Approach for Fast Electromigration Stress Analysis in Multi-Segment Interconnects. | Olympia Axelou, Nestor E. Evmorfopoulos, George Floros, George I. Stamoulis, Sachin S. Sapatnekar |
| 2021 | ASPDAC | Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks. | Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar |
| 2021 | ASPDAC | Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models. | Tonmoy Dhar, Jitesh Poojary, Yaguang Li, Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Susmita Dey Manasi, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar |
| 2021 | ASPDAC | DeepOpt: Optimized Scheduling of CNN Workloads for ASIC-based Systolic Deep Learning Accelerators. | Susmita Dey Manasi, Sachin S. Sapatnekar |
| 2021 | DAC | A New, Computationally Efficient "Blech Criterion" for Immortality in General Interconnects. | Mohammad Abdullah Al Shohel, Vidya A. Chhabria, Sachin S. Sapatnekar |
| 2021 | DATE | MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification. | Vidya A. Chhabria, Yanqing Zhang, Haoxing Ren, Ben Keller, Brucek Khailany, Sachin S. Sapatnekar |
| 2021 | DATE | Analog Layout Generation using Optimized Primitives. | Meghna Madhusudan, Arvind K. Sharma, Yaguang Li, Jiang Hu, Sachin S. Sapatnekar, Ramesh Hajiani |
| 2021 | DATE | Common-Centroid Layouts for Analog Circuits: Advantages and Limitations. | Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Parijat Mukherjee, Soner Yaldiz, Ramesh Harjani, Sachin S. Sapatnekar |
| 2021 | ICCAD | BeGAN: Power Grid Benchmark Generation Using a Process-portable GAN-based Methodology. | Vidya A. Chhabria, Kishor Kunal, Masoud Zabihi, Sachin S. Sapatnekar |
| 2021 | ICCAD | VeriGOOD-ML: An Open-Source Flow for Automated ML Hardware Synthesis. | Hadi Esmaeilzadeh, Soroush Ghodrati, Jie Gu, Shiyu Guo, Andrew B. Kahng, Joon Kyung Kim, Sean Kinzer, Rohan Mahapatra, Susmita Dey Manasi, Edwin Mascarenhas, Sachin S. Sapatnekar, Ravi Varadarajan, Zhiang Wang, Hanyang Xu, Brahmendra Reddy Yatham, Ziqing Zeng |
| 2021 | ICCAD | From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning. | Juzheng Liu, Shiyu Su, Meghna Madhusudan, Mohsen Hassanpourghadi, Samuel Saunders, Qiaochu Zhang, Rezwan A. Rasul, Yaguang Li, Jiang Hu, Arvind Kumar Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Anthony Levi, Sandeep Gupta, Mike Shuo-Wei Chen |
| 2021 | ICCAD | Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog Circuits. | Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Soner Yaldiz, Parijat Mukherjee, Ramesh Harjani, Sachin S. Sapatnekar |
| 2021 | ICCAD | Analytical Modeling of Transient Electromigration Stress based on Boundary Reflections. | Mohammad Abdullah Al Shohel, Vidya A. Chhabria, Nestor E. Evmorfopoulos, Sachin S. Sapatnekar |
| 2020 | ASPDAC | Template-based PDN Synthesis in Floorplan and Placement Using Classifier and CNN Techniques. | Vidya A. Chhabria, Andrew B. Kahng, Minsoo Kim, Uday Mallappa, Sachin S. Sapatnekar, Bangqi Xu |
| 2020 | DAC | CRAFFT: High Resolution FFT Accelerator In Spintronic Computational RAM. | M. Hsrev Cilasun, Salonik Resch, Zamshed Iqbal Chowdhury, Erin Olson, Masoud Zabihi, Zhengyang Zhao, Thomas Peterson, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu |
| 2020 | DATE | GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits. | Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar |
| 2020 | ICCAD | The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk). | Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar |
| 2020 | ICCAD | A general approach for identifying hierarchical symmetry constraints for analog circuit layout. | Kishor Kunal, Jitesh Poojary, Tonmoy Dhar, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar |
| 2020 | ICCAD | A Customized Graph Neural Network Model for Guiding Analog IC Placement. | Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu |
| 2020 | MICRO | MOUSE: Inference In Non-volatile Memory for Energy Harvesting Applications. | Salonik Resch, S. Karen Khatamifard, Zamshed I. Chowdhury, Masoud Zabihi, Zhengyang Zhao, M. Hsrev Cilasun, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu |
| 2019 | ASPDAC | SeFAct: selective feature activation and early classification for CNNs. | Farhana Sharmin Snigdha, Ibrahim Ahmed, Susmita Dey Manasi, Meghna G. Mankalale, Jiang Hu, Sachin S. Sapatnekar |
| 2019 | DAC | Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project. | Tutu Ajayi, Vidya A. Chhabria, Mateus Fogaa, Soheil Hashemi, Abdelrahman Hosny, Andrew B. Kahng, Minsoo Kim, Jeongsup Lee, Uday Mallappa, Marina Neseem, Geraldo Pradipta, Sherief Reda, Mehdi Saligane, Sachin S. Sapatnekar, Carl Sechen, Mohamed Shalan, William Swartz, Lutong Wang, Zhehong Wang, Mingyu Woo, Bangqi Xu |
| 2019 | DAC | ALIGN: Open-Source Analog Layout Automation from the Ground Up. | Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Sachin S. Sapatnekar |
| 2019 | DATE | An Energy Efficient Non-Volatile Flip-Flop based on CoMET Technology. | Robert Perricone, Zhaoxin Liang, Meghna G. Mankalale, Michael T. Niemier, Sachin S. Sapatnekar, Jianping Wang, Xiaobo Sharon Hu |
| 2019 | IPCCC | Using DCT-based Approximate Communication to Improve MPI Performance in Parallel Clusters. | Qianqian Fan, David J. Lilja, Sachin S. Sapatnekar |
| 2019 | RTCSA | Improving QoS for Global Dual-Criticality Scheduling on Multiprocessors. | Lin Huang, I-Hong Hou, Sachin S. Sapatnekar, Jiang Hu |
| 2018 | DAC | Using imprecise computing for improved non-preemptive real-time scheduling. | Lin Huang, Youmeng Li, Sachin S. Sapatnekar, Jiang Hu |
| 2018 | DATE | Computing-in-memory with spintronics. | Shubham Jain, Sachin S. Sapatnekar, Jianping Wang, Kaushik Roy, Anand Raghunathan |
| 2018 | ICCAD | Strain-aware performance evaluation and correction for OTFT-based flexible displays. | Tengtao Li, Sachin S. Sapatnekar |
| 2018 | RTNS | Graceful Degradation of Low-Criticality Tasks in Multiprocessor Dual-Criticality Systems. | Lin Huang, I-Hong Hou, Sachin S. Sapatnekar, Jiang Hu |
| 2017 | CASES | A quantifiable approach to approximate computing: special session. | Chaofan Li, Deepashree Sengupta, Farhana Sharmin Snigdha, Wenbin Xu, Jiang Hu, Sachin S. Sapatnekar |
| 2017 | DAC | Incorporating the Role of Stress on Electromigration in Power Grids with Via Arrays. | Vivek Mishra, Palkesh Jain, Sravan K. Marella, Sachin S. Sapatnekar |
| 2017 | DAC | SABER: Selection of Approximate Bits for the Design of Error Tolerant Circuits. | Deepashree Sengupta, Farhana Sharmin Snigdha, Jiang Hu, Sachin S. Sapatnekar |
| 2017 | DAC | A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited. | Jianping Wang, Sachin S. Sapatnekar, Chris H. Kim, Paul A. Crowell, Steven J. Koester, Supriyo Datta, Kaushik Roy, Anand Raghunathan, Xiaobo Sharon Hu, Michael T. Niemier, Azad Naeemi, Chia-Ling Chien, Caroline A. Ross, Roland Kawakami |
| 2017 | DATE | Advanced spintronic memory and logic for non-volatile processors. | Robert Perricone, Ibrahim Ahmed, Zhaoxin Liang, Meghna G. Mankalale, Xiaobo Sharon Hu, Chris H. Kim, Michael T. Niemier, Sachin S. Sapatnekar, Jianping Wang |
| 2017 | ICCAD | Stress-aware performance evaluation of 3D-stacked wide I/O DRAMs. | Tengtao Li, Sachin S. Sapatnekar |
| 2017 | ISLPED | A simple yet efficient accuracy configurable adder design. | Wenbin Xu, Sachin S. Sapatnekar, Jiang Hu |
| 2016 | ASPDAC | Logic and memory design using spin-based circuits. | Zhaoxin Liang, Meghna G. Mankalale, Brandon Del Bel, Sachin S. Sapatnekar |
| 2016 | DAC | Predicting electromigration mortality under temperature and product lifetime specifications. | Vivek Mishra, Sachin S. Sapatnekar |
| 2016 | DAC | Invited - Optimizing device reliability effects at the intersection of physics, circuits, and architecture. | Deepashree Sengupta, Vivek Mishra, Sachin S. Sapatnekar |
| 2016 | DAC | Optimal design of JPEG hardware under the approximate computing paradigm. | Farhana Sharmin Snigdha, Deepashree Sengupta, Jiang Hu, Sachin S. Sapatnekar |
| 2016 | ICCAD | Control synthesis and delay sensor deployment for efficient ASV designs. | Chaofan Li, Sachin S. Sapatnekar, Jiang Hu |
| 2015 | ASPDAC | A retargetable and accurate methodology for logic-IP-internal electromigration assessment. | Palkesh Jain, Sachin S. Sapatnekar, Jordi Cortadella |
| 2015 | DAC | Joint precision optimization and high level synthesis for approximate computing. | Chaofan Li, Wei Luo, Sachin S. Sapatnekar, Jiang Hu |
| 2015 | ICCAD | Optimization of FinFET-based circuits using a dual gate pitch technique. | Sravan K. Marella, Amit Ranjan Trivedi, Saibal Mukhopadhyay, Sachin S. Sapatnekar |
| 2015 | ICCAD | FEMTO: Fast Error Analysis in Multipliers through Topological Traversal. | Deepashree Sengupta, Sachin S. Sapatnekar |
| 2015 | ICCD | Reactive clocks with variability-tracking jitter. | Jordi Cortadella, Luciano Lavagno, Pedro Lopez, Marc Lupon, Alberto Moreno, Antoni Roca, Sachin S. Sapatnekar |
| 2014 | ASPDAC | Predicting circuit aging using ring oscillators. | Deepashree Sengupta, Sachin S. Sapatnekar |
| 2014 | DATE | Improving STT-MRAM density through multibit error correction. | Brandon Del Bel, Jongyeon Kim, Chris H. Kim, Sachin S. Sapatnekar |
| 2014 | ICCAD | A systematic approach for analyzing and optimizing cell-internal signal electromigration. | Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar |
| 2014 | ICCAD | ReSCALE: recalibrating sensor circuits for aging and lifetime estimation under BTI. | Deepashree Sengupta, Sachin S. Sapatnekar |
| 2014 | VLSID | Leakage Modeling for Devices with Steep Sub-threshold Slope Considering Random Threshold Variations. | Ayan Paul, Chaitanya Kshirsagar, Sachin S. Sapatnekar, Steven J. Koester, Chris H. Kim |
| 2013 | DAC | The impact of electromigration in copper interconnects on power grid integrity. | Vivek Mishra, Sachin S. Sapatnekar |
| 2013 | DATE | CATALYST: planning layer directives for effective design closure. | Yaoguang Wei, Zhuo Li, Cliff C. N. Sze, Shiyan Hu, Charles J. Alpert, Sachin S. Sapatnekar |
| 2013 | DATE | Placement optimization of power supply pads based on locality. | Pingqiang Zhou, Vivek Mishra, Sachin S. Sapatnekar |
| 2013 | ICCAD | The impact of shallow trench isolation effects on circuit performance. | Sravan K. Marella, Sachin S. Sapatnekar |
| 2012 | ASPDAC | Incremental power network analysis using backward random walks. | Baktash Boghrati, Sachin S. Sapatnekar |
| 2012 | ASPDAC | The impact of hot carriers on timing in large circuits. | Jianxin Fang, Sachin S. Sapatnekar |
| 2012 | ASPDAC | GNOMO: Greater-than-NOMinal Vdd operation for BTI mitigation. | Saket Gupta, Sachin S. Sapatnekar |
| 2012 | ASPDAC | BTI-aware design using variable latency units. | Saket Gupta, Sachin S. Sapatnekar |
| 2012 | DAC | GLARE: global and local wiring aware routability evaluation. | Yaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Tllez, Douglas Keller, Sachin S. Sapatnekar |
| 2012 | ICCAD | Circuit reliability: From Physics to Architectures: Embedded tutorial paper. | Jianxin Fang, Saket Gupta, Sanjay V. Kumar, Sravan K. Marella, Vivek Mishra, Pingqiang Zhou, Sachin S. Sapatnekar |
| 2012 | ICCAD | A holistic analysis of circuit timing variations in 3D-ICs with thermal and TSV-induced stress considerations. | Sravan K. Marella, Sanjay V. Kumar, Sachin S. Sapatnekar |
| 2012 | ICCAD | Optimization of on-chip switched-capacitor DC-DC converters for high-performance applications. | Pingqiang Zhou, Won Ho Choi, Bongjin Kim, Chris H. Kim, Sachin S. Sapatnekar |
| 2012 | ISLPED | Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems. | Jieming Yin, Pingqiang Zhou, Anup Holey, Sachin S. Sapatnekar, Antonia Zhai |
| 2011 | ASPDAC | Accounting for inherent circuit resilience and process variations in analyzing gate oxide reliability. | Jianxin Fang, Sachin S. Sapatnekar |
| 2011 | DAC | Thermal signature: a simple yet accurate thermal index for floorplan optimization. | Jaeha Kung, Inhak Han, Sachin S. Sapatnekar, Youngsoo Shin |
| 2011 | DATE | A scaled random walk solver for fast power grid analysis. | Baktash Boghrati, Sachin S. Sapatnekar |
| 2011 | DATE | Enabling improved power management in multicore processors through clustered DVFS. | T. Kolpe, Antonia Zhai, Sachin S. Sapatnekar |
| 2011 | ISLPED | The whys and hows of thermal management. | Sachin S. Sapatnekar |
| 2011 | ISLPED | NoC frequency scaling with flexible-pipeline routers. | Pingqiang Zhou, Jieming Yin, Antonia Zhai, Sachin S. Sapatnekar |
| 2010 | ASPDAC | Incremental solution of power grids using random walks. | Baktash Boghrati, Sachin S. Sapatnekar |
| 2010 | ASPDAC | Current source modeling in the presence of body bias. | Saket Gupta, Sachin S. Sapatnekar |
| 2010 | ASPDAC | Physical design techniques for optimizing RTA-induced variations. | Yaoguang Wei, Jiang Hu, Frank Liu, Sachin S. Sapatnekar |
| 2010 | ASPDAC | Application-specific 3D Network-on-Chip design using simulated allocation. | Pingqiang Zhou, Ping-Hung Yuh, Sachin S. Sapatnekar |
| 2010 | ICCAD | Fast Poisson solvers for thermal analysis. | Haifeng Qian, Sachin S. Sapatnekar |
| 2009 | ASPDAC | Adaptive techniques for overcoming performance degradation due to aging in digital circuits. | Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar |
| 2009 | ASPDAC | Addressing thermal and power delivery bottlenecks in 3D circuits. | Sachin S. Sapatnekar |
| 2009 | ASPDAC | Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors. | Pingqiang Zhou, Karthikk Sridharan, Sachin S. Sapatnekar |
| 2008 | DAC | A framework for block-based timing sensitivity analysis. | Sanjay V. Kumar, Chandramouli V. Kashyap, Sachin S. Sapatnekar |
| 2008 | DAC | Reinventing EDA with manycore processors. | Sachin S. Sapatnekar, Eshel Haritan, Kurt Keutzer, Anirudh Devgan, Desmond Kirkpatrick, Stephen Meier, Duaine Pryor, Tom Spyrou |
| 2008 | DAC | A progressive-ILP based routing algorithm for cross-referencing biochips. | Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang |
| 2007 | DAC | Placement of 3D ICs with Thermal and Interlayer Via Considerations. | Brent Goplen, Sachin S. Sapatnekar |
| 2007 | DAC | Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift. | Jie Gu, Sachin S. Sapatnekar, Chris H. Kim |
| 2007 | DAC | NBTI-Aware Synthesis of Digital Circuits. | Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar |
| 2007 | DAC | Confidence Scalable Post-Silicon Statistical Delay Prediction under Process Variations. | Qunzeng Liu, Sachin S. Sapatnekar |
| 2007 | ICCAD | A general model for performance optimization of sequential systems. | Dmitry Bufistov, Jordi Cortadella, Michael Kishinevsky, Sachin S. Sapatnekar |
| 2007 | ICCAD | Clustering based pruning for statistical criticality computation under process variations. | Hushrav Mogal, Haifeng Qian, Sachin S. Sapatnekar, Kia Bazargan |
| 2007 | ICCAD | Module assignment for pin-limited designs under the stacked-Vdd paradigm. | Yong Zhan, Tianpei Zhang, Sachin S. Sapatnekar |
| 2006 | ASPDAC | Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systems. | Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar |
| 2006 | ASPDAC | A fixed-die floorplanning algorithm using an analytical approach. | Yong Zhan, Yan Feng, Sachin S. Sapatnekar |
| 2006 | ASPDAC | Electrothermal analysis and optimization techniques for nanoscale integrated circuits. | Yong Zhan, Brent Goplen, Sachin S. Sapatnekar |
| 2006 | ASPDAC | Temperature-aware routing in 3D ICs. | Tianpei Zhang, Yong Zhan, Sachin S. Sapatnekar |
| 2006 | DAC | Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing. | John Keane, Hanyong Eom, Tony Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim |
| 2006 | DAC | Statistical timing analysis with correlated non-gaussian parameters using independent component analysis. | Jaskirat Singh, Sachin S. Sapatnekar |
| 2006 | ICCAD | An analytical model for negative bias temperature instability. | Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar |
| 2006 | ISLPED | Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysis. | Vidyasagar Nookala, David J. Lilja, Sachin S. Sapatnekar |
| 2006 | ISPASS | Comparing simulation techniques for microarchitecture-aware floorplanning. | Vidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar |
| 2005 | ASPDAC | Buffering global interconnects in structured ASIC design. | Tianpei Zhang, Sachin S. Sapatnekar |
| 2005 | ASPDAC | Fast computation of the temperature distribution in VLSI chips using the discrete cosine transform and table look-up. | Yong Zhan, Sachin S. Sapatnekar |
| 2005 | DAC | Full-chip analysis of leakage power under process variations, including spatial correlations. | Hongliang Chang, Sachin S. Sapatnekar |
| 2005 | DAC | Net weighting to reduce repeater counts during placement. | Brent Goplen, Prashant Saxena, Sachin S. Sapatnekar |
| 2005 | DAC | Microarchitecture-aware floorplanning using a statistical design of experiments approach. | Vidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar |
| 2005 | DAC | Robust gate sizing by geometric programming. | Jaskirat Singh, Vidyasagar Nookala, Zhi-Quan Luo, Sachin S. Sapatnekar |
| 2005 | ICCAD | A hybrid linear equation solver and its application in quadratic placement. | Haifeng Qian, Sachin S. Sapatnekar |
| 2005 | ICCAD | A high efficiency full-chip thermal simulation algorithm. | Yong Zhan, Sachin S. Sapatnekar |
| 2005 | ICCD | Exact lower bound for the number of switches in series to implement a combinational logic cell. | Felipe Ribeiro Schneider, Renato P. Ribas, Sachin S. Sapatnekar, Andr Incio Reis |
| 2005 | ISCAS | Fast estimation of area-delay trade-offs in circuit sizing. | Shrirang K. Karandikar, Sachin S. Sapatnekar |
| 2005 | ISCAS | Designing optimized pipelined global interconnects: algorithms and methodology impact. | Vidyasagar Nookala, Sachin S. Sapatnekar |
| 2005 | VLSID | High-Speed Interconnect Technology: On-Chip and Off-Chip. | Sachin S. Sapatnekar, Jaijeet S. Roychowdhury, Ramesh Harjani |
| 2004 | ASPDAC | Hierarchical random-walk algorithms for power grid analysis. | Haifeng Qian, Sachin S. Sapatnekar |
| 2004 | DAC | A method for correcting the functionality of a wire-pipelined circuit. | Vidyasagar Nookala, Sachin S. Sapatnekar |
| 2004 | DAC | Tradeoffs between date oxide leakage and delay for dual T | Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar |
| 2004 | DATE | Fast Comparisons of Circuit Implementations. | Shrirang K. Karandikar, Sachin S. Sapatnekar |
| 2004 | DATE | Optimization of Integrated Spiral Inductors Using Sequential Quadratic Programming. | Yong Zhan, Sachin S. Sapatnekar |
| 2004 | ICCAD | Accurate estimation of global buffer delay within a floorplan. | Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze |
| 2004 | ICCAD | Logical effort based technology mapping. | Shrirang K. Karandikar, Sachin S. Sapatnekar |
| 2004 | ICCAD | A chip-level electrostatic discharge simulation strategy. | Haifeng Qian, Joseph N. Kozhaya, Sani R. Nassif, Sachin S. Sapatnekar |
| 2004 | ICCD | Transistor and Pin Reordering for Gate Oxide Leakage Reduction in Dual T{ox} Circuits. | Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar |
| 2004 | ICCD | Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing. | Tianpei Zhang, Sachin S. Sapatnekar |
| 2004 | VLSID | High-Performance Power Grids For Nanometer Technologies. | Sachin S. Sapatnekar |
| 2003 | DAC | Random walks in a supply network. | Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar |
| 2003 | ICCAD | Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal. | Hongliang Chang, Sachin S. Sapatnekar |
| 2003 | ICCAD | Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach. | Brent Goplen, Sachin S. Sapatnekar |
| 2003 | ICCD | An Efficient Algorithm for Calculating the Worst-case Delay due to Crosstalk. | Venkatesan Rajappan, Sachin S. Sapatnekar |
| 2003 | ISCAS | Table look-up based compact modeling for on-chip interconnect timing and noise analysis. | Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar |
| 2002 | DAC | Congestion-driven codesign of power and signal networks. | Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif |
| 2002 | ICCAD | A precorrected-FFT method for simulating on-chip inductance. | Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar |
| 2002 | ICCAD | Standby power optimization via transistor sizing and dual threshold voltage assignment. | Mahesh Ketkar, Sachin S. Sapatnekar |
| 2002 | ICCD | Efficient PEEC-Based Inductance Extraction Using Circuit-Aware Techniques. | Haitian Hu, Sachin S. Sapatnekar |
| 2002 | VLSID | An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis. | Rupesh S. Shelar, Sachin S. Sapatnekar |
| 2001 | DAC | A Practical Methodology for Early Buffer and Wire Resource Allocation. | Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia |
| 2001 | DAC | Technology Mapping for SOI Domino Logic Incorporating Solutions for the Parasitic Bipolar Effect. | Shrirang K. Karandikar, Sachin S. Sapatnekar |
| 2001 | DAC | A New Structural Pattern Matching Algorithm for Technology Mapping. | Min Zhao, Sachin S. Sapatnekar |
| 2001 | ICCAD | Recursive Bipartitioning of BDDs for Performance Driven Synthesis of Pass Transistor Logic Circuits. | Rupesh S. Shelar, Sachin S. Sapatnekar |
| 2001 | ICCAD | Hybrid Structured Clock Network Construction. | Haihua Su, Sachin S. Sapatnekar |
| 2001 | ICCD | Performance Driven Global Routing Through Gradual Refinement. | Jiang Hu, Sachin S. Sapatnekar |
| 2001 | ISCAS | Steiner tree optimization for buffers. Blockages and bays. | Charles J. Alpert, Gopal Gandham, Jiang Hu, Jos Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar |
| 2001 | VLSID | Optimization and Analysis Techniques for the Deep Submicron Regime. | Noel Menezes, Sachin S. Sapatnekar |
| 2000 | DAC | Convex delay models for transistor sizing. | Mahesh Ketkar, Kishore Kasamsetty, Sachin S. Sapatnekar |
| 2000 | DAC | MINFLOTRANSIT: min-cost flow based transistor sizing tool. | Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi |
| 2000 | DAC | Hierarchical analysis of power distribution networks. | Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, Tim Edwards, Rajat Chaudhry, David T. Blaauw |
| 2000 | ICCAD | A Timing-Constrained Algorithm for Simultaneous Global Routing of Multiple Nets. | Jiang Hu, Sachin S. Sapatnekar |
| 2000 | ICCAD | Fast Analysis and Optimization of Power/Ground Networks. | Haihua Su, Kaushik Gala, Sachin S. Sapatnekar |
| 2000 | ISCAS | Dual-monotonic domino gate mapping and optimal output phase assignment of domino logic. | Min Zhao, Sachin S. Sapatnekar |
| 2000 | VLSID | Capturing the Effect of Crosstalk on Delay. | Sachin S. Sapatnekar |
| 1999 | DAC | FAR-DS: Full-Plane AWE Routing with Driver Sizing. | Jiang Hu, Sachin S. Sapatnekar |
| 1999 | ICCAD | An integrated algorithm for combined placement and libraryless technology mapping. | Yanbin Jiang, Sachin S. Sapatnekar |
| 1999 | ICCAD | Marsh: min-area retiming with setup and hold constraints. | Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi |
| 1999 | ICCAD | Timing-driven partitioning for two-phase domino and mixed static/domino implementations. | Min Zhao, Sachin S. Sapatnekar |
| 1999 | ICCD | Efficient Crosstalk Estimation. | Martin Kuhlmann, Sachin S. Sapatnekar, Keshab K. Parhi |
| 1999 | ISLPED | Clock distribution using multiple voltages. | Jatuchai Pangjun, Sachin S. Sapatnekar |
| 1998 | DATE | Efficient Minarea Retiming of Large Level-Clocked Circuits. | Naresh Maheshwari, Sachin S. Sapatnekar |
| 1998 | ICCAD | Technology mapping for domino logic. | Min Zhao, Sachin S. Sapatnekar |
| 1998 | ICCD | A fast global gate collapsing technique for high performance designs using static CMOS and pass transistor logic. | Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji |
| 1997 | DAC | An Improved Algorithm for Minimum-Area Retiming. | Naresh Maheshwari, Sachin S. Sapatnekar |
| 1997 | ICCAD | Minimum area retiming with equivalent initial states. | Naresh Maheshwari, Sachin S. Sapatnekar |
| 1996 | ICCAD | Clock tree synthesis for multi-chip modules. | Daksh Lehther, Sachin S. Sapatnekar |
| 1996 | ICCD | A Practical Algorithm for Retiming Level-Clocked Circuits. | Naresh Maheshwari, Sachin S. Sapatnekar |
| 1996 | VLSID | Wiresizing with Buffer Placement and Sizing for Power-Delay Tradeoffs. | Jatan C. Shah, Sachin S. Sapatnekar |
| 1995 | DAC | A Fresh Look at Retiming Via Clock Skew Optimization. | Rahul B. Deokar, Sachin S. Sapatnekar |
| 1995 | ICCAD | Power vs. delay in gate sizing: conflicting objectives? | Sachin S. Sapatnekar, Weitong Chuang |
| 1995 | ICCAD | Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. | Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn |
| 1995 | ISCAS | Layout Optimization Using Arbitrarily High Degree Posynomial Models. | Piyush K. Sancheti, Sachin S. Sapatnekar |
| 1994 | DAC | RC Interconnect Optimization Under the Elmore Delay Model. | Sachin S. Sapatnekar |
| 1994 | ICPP | A Convex Programming Approach for Exploiting Data and Functional Parallelism on Distributed Memory Multicomputers. | Shankar Ramaswamy, Sachin S. Sapatnekar, Prithviraj Banerjee |
| 1994 | ISCAS | A Graph-Theoretic Approach to Clock Skew Optimization. | Rahul B. Deokar, Sachin S. Sapatnekar |
| 1994 | ISCAS | High Performance CMOS Macromodule Layout Synthesis. | Jaewon Kim, Sung-Mo Kang, Sachin S. Sapatnekar |
| 1993 | ICCAD | A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area. | Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj |
| 1993 | ICCAD | Convexity-based algorithms for design centering. | Sachin S. Sapatnekar, Pravin M. Vaidya, Steve M. Kang |
| 1993 | ISCAS | Feasible Region Approximation Using Convex Polytopes. | Sachin S. Sapatnekar, Pravin M. Vaidya, Sung-Mo Kang |
| 1991 | ICCAD | A Convex Optimization Approach to Transistor Sizing for CMOS Circuits. | Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya |