| 2005 | A Wide-Swing V_T-Referenced Circuit with Insensitivity to Device Mismatch. | Chih-Jen Yen, Wen-Yaw Chung, Mely Chen Chi |
| 2005 | A Delay Test to Differentiate Resistive Interconnect Faults from Weak Transistor Defects. | Haihua Yan, Adit D. Singh |
| 2005 | Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits. | Shengqi Yang, Wayne H. Wolf, Narayanan Vijaykrishnan, Yuan Xie, Wenping Wang |
| 2005 | Optimization of Mixed Logic Circuits with Application to a 64-Bit Static Adder. | Yuanzhong Wan, Maitham Shams |
| 2005 | Multivariate Normal Distribution Based Statistical Timing Analysis Using Global Projection and Local Expansion. | Baohua Wang, Pinaki Mazumder |
| 2005 | Algorithmic Implementation of Low-Power High Performance FIR Filtering IP Cores. | C. H. Wang, Ahmet T. Erdogan, Tughrul Arslan |
| 2005 | A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model. | Yibo Wang, Yici Cai, Xianlong Hong |
| 2005 | 65nm Omnibudsman. | Ted Vucurevich |
| 2005 | Power Switch Network Design for MTCMOS. | Ramaprasath Vilangudipitchai, Poras T. Balsara |
| 2005 | Impact of Process Variations on Multi-Level Signaling for On-Chip Interconnects. | Vishak Venkatraman, Wayne P. Burleson |
| 2005 | An Efficient Methodology for Noise Characterization. | Gaurav Kumar Varshney, Sreeram Chandrasekar |
| 2005 | Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty. | Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin |
| 2005 | False Path and Clock Scheduling Based Yield-Aware Gate Sizing. | Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja |
| 2005 | Implementing LDPC Decoding on Network-on-Chip. | Theo Theocharides, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin |
| 2005 | Evaluation of Speed and Area of Clustered VLIW Processors. | Andrei Sergeevich Terechko, Manish Garg, Henk Corporaal |
| 2005 | On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios. | Huaxing Tang, Chen Wang, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Irith Pomeranz |
| 2005 | Behavioral Synthesis of Data-Dominated Circuits for Minimal Energy Implementation. | Xiaoyong Tang, Tianyi Jiang, Alex K. Jones, Prithviraj Banerjee |
| 2005 | Application of Alpha Power Law Models to PLL Design Methodology. | B. Suresh, V. Visvanathan, R. S. Krishnan, H. S. Jamadagni |
| 2005 | Worst-Case Crosstalk Noise Analysis Based on Dual-Exponential Noise Metrics. | Jiaxing Sun, Yun Zheng, Qing Ye, Tianchun Ye |
| 2005 | Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors. | Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
| 2005 | An Accurate Energy and Thermal Model for Global Signal Buses. | Krishnan Sundaresan, Nihar R. Mahapatra |
| 2005 | ISIS: A Genetic Algorithm Based Technique for Custom On-Chip Interconnection Network Synthesis. | Krishnan Srinivasan, Karam S. Chatha |
| 2005 | Impact of Channel Engineering on Unity Gain Frequency and Noise-Figure in 90nm NMOS Transistor for RF Applications. | R. Srinivasan, Navakanta Bhat |
| 2005 | Coding for Reliable On-Chip Buses: Fundamental Limits and Practical Codes. | Srinivasa R. Sridhara, Naresh R. Shanbhag |
| 2005 | A Hierarchical Cost Tree Mutation Approach to Optimization of Analog Circuits. | Abhishek Somani, P. P. Chakrabarti, Amit Patra |