| 2025 | ISCAS | Low-Power Continuous Wavelet Transform Employing Stochastic Computing. | Roshwin Sengupta, Ilia Polian, John P. Hayes |
| 2024 | DDECS | Performance and Error Tolerance of Stochastic Computing-Based Digital Filter Design. | Roshwin Sengupta, Ilia Polian, John P. Hayes |
| 2023 | DATE | Design of Large-Scale Stochastic Computing Adders and their Anomalous Behavior. | Timothy J. Baker, John P. Hayes |
| 2023 | DSN | Stochastic Computing as a Defence Against Adversarial Attacks. | Florian Neugebauer, Vivek Vekariya, Ilia Polian, John P. Hayes |
| 2022 | DDECS | Analyzing Multilevel Stochastic Circuits using Correlation Matrices. | Owen Hoffend, John P. Hayes |
| 2022 | DDECS | Stochastic Computing Architectures for Lightweight LSTM Neural Networks. | Roshwin Sengupta, Ilia Polian, John P. Hayes |
| 2022 | ISCAS | Wavelet Transform Assisted Neural Networks for Human Activity Recognition. | Roshwin Sengupta, Ilia Polian, John P. Hayes |
| 2020 | DATE | The Hypergeometric Distribution as a More Accurate Model for Stochastic Computing. | Timothy J. Baker, John P. Hayes |
| 2020 | ICCAD | Bayesian Accuracy Analysis of Stochastic Circuits. | Timothy J. Baker, John P. Hayes |
| 2020 | ICCAD | Exploring Target Function Approximation for Stochastic Circuit Minimization. | Chen Wang, Weihua Xiao, John P. Hayes, Weikang Qian |
| 2020 | ICCD | Hardware-based Fast Real-time Image Classification with Stochastic Computing. | Ponnanna Kelettira Muthappa, Florian Neugebauer, Ilia Polian, John P. Hayes |
| 2019 | ICCAD | Exploiting Randomness in Stochastic Computing. | Pai-Shun Ting, John P. Hayes |
| 2017 | DATE | Energy-efficient hybrid stochastic-binary neural networks for near-sensor computing. | Vincent T. Lee, Armin Alaghi, John P. Hayes, Visvesh Sathe, Luis Ceze |
| 2017 | DATE | Framework for quantifying and managing accuracy in stochastic circuit design. | Florian Neugebauer, Ilia Polian, John P. Hayes |
| 2017 | DSD | Building a Better Random Number Generator for Stochastic Computing. | Florian Neugebauer, Ilia Polian, John P. Hayes |
| 2017 | ICCAD | Design of accurate stochastic number generators with noisy emerging devices for stochastic computing. | Meng Yang, John P. Hayes, Deliang Fan, Weikang Qian |
| 2016 | ICCD | Isolation-based decorrelation of stochastic circuits. | Pai-Shun Ting, John P. Hayes |
| 2015 | DAC | Equivalence among stochastic logic circuits and its application. | Te-Hsuan Chen, John P. Hayes |
| 2015 | DAC | Introduction to stochastic computing and its challenges. | John P. Hayes |
| 2015 | DDECS | Low-Area and High-Speed Approximate Matrix-Vector Multiplier. | I-Che Chen, John P. Hayes |
| 2015 | ICCAD | Optimizing Stochastic Circuits for Accuracy-Energy Tradeoffs. | Armin Alaghi, Wei-Ting Jonas Chan, John P. Hayes, Andrew B. Kahng, Jiajia Li |
| 2014 | DATE | Fast and accurate computation using stochastic circuits. | Armin Alaghi, John P. Hayes |
| 2014 | ICCD | Analyzing and controlling accuracy in stochastic circuits. | Te-Hsuan Chen, John P. Hayes |
| 2013 | DAC | Stochastic circuits for real-time image-processing applications. | Armin Alaghi, Cheng Li, John P. Hayes |
| 2013 | DDECS | Design of stochastic Viterbi decoders for convolutional codes. | Te-Hsuan Chen, John P. Hayes |
| 2013 | ICCD | Exploiting correlation in stochastic circuit design. | Armin Alaghi, John P. Hayes |
| 2012 | ASPDAC | Detection and diagnosis of faulty quantum circuits. | Alexandru Paler, Ilia Polian, John P. Hayes |
| 2012 | ICCAD | Scalable sampling methodology for logic simulation: Reduced-Ordered Monte Carlo. | Chien-Chih Yu, Armin Alaghi, John P. Hayes |
| 2012 | ICCD | A spectral transform approach to stochastic circuits. | Armin Alaghi, John P. Hayes |
| 2011 | DATE | Trigonometric method to handle realistic error probabilities in logic circuits. | Chien-Chih Yu, John P. Hayes |
| 2011 | DDECS | Wireless wafer-level testing of integrated circuits via capacitively-coupled channels. | Dae Young Lee, David D. Wentzloff, John P. Hayes |
| 2011 | ETS | Tomographic Testing and Validation of Probabilistic Circuits. | Alexandru Paler, Armin Alaghi, Ilia Polian, John P. Hayes |
| 2010 | FPGA | On-line sensing for healthier FPGA systems. | Kenneth M. Zick, John P. Hayes |
| 2010 | FPL | Self-Test and Adaptation for Random Variations in Reliability. | Kenneth M. Zick, John P. Hayes |
| 2010 | VTS | Scalable and accurate estimation of probabilistic behavior in sequential circuits. | Chien-Chih Yu, John P. Hayes |
| 2009 | DAC | Improving testability and soft-error resilience through retiming. | Smita Krishnaswamy, Igor L. Markov, John P. Hayes |
| 2009 | DATE | Contactless testing: Possibility or pipe-dream? | Erik Jan Marinissen, Dae Young Lee, John P. Hayes, Chris Sellathamby, Brian Moore, Steven Slupsky, Laurence Pujol |
| 2009 | IOLTS | On-line characterization and reconfiguration for single event upset variations. | Kenneth M. Zick, John P. Hayes |
| 2008 | DAC | On the role of timing masking in reliable logic circuit design. | Smita Krishnaswamy, Igor L. Markov, John P. Hayes |
| 2008 | LCN | Optimizing router locations for minimum-energy wireless networks. | Sungsoon Cho, John P. Hayes |
| 2007 | ICCAD | Enhancing design robustness with reliability-aware resynthesis and logic simulation. | Smita Krishnaswamy, Stephen Plaza, Igor L. Markov, John P. Hayes |
| 2007 | ICCAD | Checking equivalence of quantum circuits and states. | George F. Viamontes, Igor L. Markov, John P. Hayes |
| 2007 | LCN | Power-Aware Link Maintenance (PALM) for Mobile Ad Hoc Networks. | Sungsoon Cho, John P. Hayes |
| 2007 | VTS | An Analysis Framework for Transient-Error Tolerance. | John P. Hayes, Ilia Polian, Bernd Becker |
| 2006 | ETS | On-Chip Test Generation Using Linear Subspaces. | Ramashis Das, Igor L. Markov, John P. Hayes |
| 2005 | DAC | Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages. | Feng Gao, John P. Hayes |
| 2005 | DATE | Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices. | Smita Krishnaswamy, George F. Viamontes, Igor L. Markov, John P. Hayes |
| 2005 | ETS | Logic circuit testing for transient faults. | Smita Krishnaswamy, Igor L. Markov, John P. Hayes |
| 2005 | ITC | Transient fault characterization in dynamic noisy environments. | Ilia Polian, John P. Hayes, Sandip Kundu, Bernd Becker |
| 2005 | WCNC | Impact of mobility on connection in ad hoc networks. | Sungsoon Cho, John P. Hayes |
| 2004 | DATE | High-Performance QuIDD-Based Simulation of Quantum Circuits. | George F. Viamontes, Igor L. Markov, John P. Hayes |
| 2004 | DSN | Discovering 1-FT Routes in Mobile Ad Hoc Networks. | Rajesh Venkatasubramanian, John P. Hayes |
| 2004 | ICCAD | Exact and heuristic approaches to input vector control for leakage power reduction. | Feng Gao, John P. Hayes |
| 2004 | ICCD | Gate Sizing and V{t} Assignment for Active-Mode Leakage Power Reduction. | Feng Gao, John P. Hayes |
| 2003 | ASPDAC | Gate-level simulation of quantum circuits. | George F. Viamontes, Manoj Rajagopalan, Igor L. Markov, John P. Hayes |
| 2003 | DAC | Tutorial: basic concepts in quantum circuits. | John P. Hayes |
| 2003 | IOLTS | Low-Cost On-Line Fault Detection Using Control Flow Assertions. | Rajesh Venkatasubramanian, John P. Hayes, Brian T. Murray |
| 2003 | ISLPED | ILP-based optimization of sequential circuits for low power. | Feng Gao, John P. Hayes |
| 2003 | VTS | Fault Testing for Reversible Circuits. | Ketan N. Patel, John P. Hayes, Igor L. Markov |
| 2003 | SAFECOMP | Dependable Communication Synthesis for Distributed Embedded Systems. | Nagarajan Kandasamy, John P. Hayes, Brian T. Murray |
| 2002 | DSN | Time-Constrained Failure Diagnosis in Distributed Embedded Systems. | Nagarajan Kandasamy, John P. Hayes, Brian T. Murray |
| 2002 | ICCAD | Reversible logic circuit synthesis. | Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes |
| 2002 | IOLTS | On-Line Monitor Design of Finite-State Machines. | Feng Gao, John P. Hayes |
| 2001 | DAC | An Advanced Timing Characterization Method Using Mode Dependency. | Hakan Yalcin, Robert Palermo, Mohammad Mortazavi, Cyrus Bamji, Karem A. Sakallah, John P. Hayes |
| 2001 | ETS | A fault model for function and delay testing. | Joonhwan Yi, John P. Hayes |
| 2000 | VTS | ESIM: A Multimodel Design Error and Fault Simulator for Logic Circuits. | Hussain Al-Asaad, John P. Hayes |
| 1999 | DAC | High-Level Test Generation for Design Verification of Pipelined Microprocessors. | David Van Campenhout, Trevor N. Mudge, John P. Hayes |
| 1999 | ITC | Delay fault testing of IP-based designs via symbolic path modeling. | HyungWon Kim, John P. Hayes |
| 1999 | VLSID | Near-Optimum Hierarchical Layout Synthesis of Two-Dimensional CMOS Cells. | Avaneendra Gupta, John P. Hayes |
| 1999 | VTS | Delay Fault Testing of Designs with Embedded IP Cores. | HyungWon Kim, John P. Hayes |
| 1999 | SRDS | Tolerating Transient Faults in Statically Scheduled Safety-Critical Embedded Systems. | Nagarajan Kandasamy, John P. Hayes, Brian T. Murray |
| 1998 | ICCAD | Optimal 2-D cell layout with integrated transistor folding. | Avaneendra Gupta, John P. Hayes |
| 1998 | ITC | High-coverage ATPG for datapath circuits with unimplemented blocks. | HyungWon Kim, John P. Hayes |
| 1997 | DAC | CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells. | Avaneendra Gupta, John P. Hayes |
| 1997 | DATE | The input pattern fault model and its application. | Ronald D. Blanton, John P. Hayes |
| 1997 | FPGA | General Modeling and Technology-Mapping Technique for LUT-Based FPGAs. | Amit Chowdhary, John P. Hayes |
| 1997 | ICCD | Properties of the Input Pattern Fault Model. | Ronald D. Blanton, John P. Hayes |
| 1997 | VLSID | A Hierarchical Technique for Minimum-Width Layout of Two-Dimensional CMOS Cells. | Avaneendra Gupta, John P. Hayes |
| 1996 | DATE | XPRESS: A Cell Layout Generator with Integrated Transistor Folding. | Avaneendra Gupta, Siang-Chun The, John P. Hayes |
| 1996 | ICCAD | Width minimization of two-dimensional CMOS cells using integer programming. | Avaneendra Gupta, John P. Hayes |
| 1996 | ICCAD | An approximate timing analysis method for datapath circuits. | Hakan Yalcin, John P. Hayes, Karem A. Sakallah |
| 1996 | VTS | Design of a fast, easily testable ALU. | R. D. (Shawn) Blanton, John P. Hayes |
| 1995 | ICCAD | Design verification via simulation and automatic test pattern generation. | Hussain Al-Asaad, John P. Hayes |
| 1995 | ICCAD | Technology mapping for field-programmable gate arrays using integer programming. | Amit Chowdhary, John P. Hayes |
| 1995 | ICCAD | Hierarchical timing analysis using conditional delays. | Hakan Yalcin, John P. Hayes |
| 1995 | ITC | Optimal Space Compaction of Test Responses. | Krishnendu Chakrabarty, Brian T. Murray, John P. Hayes |
| 1995 | ITC | High-Level Test Generation Using Symbolic Scheduling. | Mark C. Hansen, John P. Hayes |
| 1995 | VTS | High-level test generation using physically-induced faults. | Mark C. Hansen, John P. Hayes |
| 1994 | DAC | DFBT: A Design-for-Testability Method Based on Balance Testing. | Krishnendu Chakrabarty, John P. Hayes |
| 1994 | ITC | Efficient Test-Response Compression for Multiple-Output Cicuits. | Krishnendu Chakrabarty, John P. Hayes |
| 1993 | VTS | Aliasing-free error detection (ALFRED). | Krishnendu Chakrabarty, John P. Hayes |
| 1992 | DAC | Test-Set Preserving Logic Transformations. | Michael J. Batek, John P. Hayes |
| 1991 | DAC | Exact Width and Height Minimization of CMOS Cells. | Robert L. Maziasz, John P. Hayes |
| 1991 | ICPP | Scalar-Vector Memory Interference in Vector Computers. | Ram Raghavan, John P. Hayes |
| 1991 | ITC | Test Propagation Through Modules and Circuits. | Brian T. Murray, John P. Hayes |
| 1990 | SC | On randomly interleaved memories. | Ram Raghavan, John P. Hayes |
| 1989 | ICCD | Magnitude classes in switch-level modeling. | Eduard Cerny, John P. Hayes, Nicholas C. Rumin |
| 1988 | ICCAD | Logic simulation on vector processors. | Ram Raghavan, John P. Hayes, William R. Martin |
| 1988 | ITC | Hierarchical Test Generation Using Precomputed Tests for Modules. | Brian T. Murray, John P. Hayes |
| 1987 | DAC | Layout Optimization of CMOS Functional Cells. | R. L. Maiasz, John P. Hayes |
| 1986 | ICPP | Architecture of a Hypercube Supercomputer. | John P. Hayes, Trevor N. Mudge, Quentin F. Stout |
| 1984 | DAC | An experimental MOS fault simulation program CSASIM. | Masato Kawai, John P. Hayes |
| 1984 | ICDCS | Distributed Recovery in Fault-Tolerant Multiprocessor Networks. | Raif M. Yanney, John P. Hayes |
| 1982 | DAC | A fault simulation methodology for VLSI. | John P. Hayes |
| 1980 | ISCA | Fault Tolerance of a Class of Connecting Networks. | John Paul Shen, John P. Hayes |
| 1976 | DAC | Partitioning logic circuits to maximize fault resolution. | Ayee Goundan, John P. Hayes |
| 1974 | FOCS | Minimization of Fanout in Switching Networks | John P. Hayes |