Jean-Luc Danger
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
99
Venues
39
Active years
1999–2026
Best venue rank
A*
Where they publish
- ADATE15 papers
- CDSD11 papers
- CFDTC9 papers
- CWISTP6 papers
- BETS4 papers
- BFPL4 papers
- BISIT3 papers
- Journal PublishedCASES3 papers
- A*ISCA3 papers
- AFPGA3 papers
- NationalVTS2 papers
- CSECRYPT2 papers
- CIOLTS2 papers
- CICCD2 papers
- ACHES2 papers
- A*DAC2 papers
- CCARDIS2 papers
- NationalINDOCRYPT2 papers
- A*MICRO2 papers
- NationalIWSEC1 paper
- CAICCSA1 paper
- BACNS1 paper
- BNCA1 paper
- AITC1 paper
- NationalVLSID1 paper
- BTrustCom1 paper
- BASPDAC1 paper
- AACSAC1 paper
- A*POPL1 paper
- CICICS1 paper
- CETFA1 paper
- MulticonferenceICASSP1 paper
- NationalICISC1 paper
- NationalWISA1 paper
- UnrankedEDCC1 paper
- BVTC1 paper
- BPIMRC1 paper
- BWCNC1 paper
- CISCAS1 paper
Papers
99 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | DATE | HEED: A Highly Efficient Electromagnetic Fault Detection Scheme. | Roukoz Nabhan, Mohammad Ebrahimabadi, Jean-Luc Danger, Jean-Max Dutertre, Sylvain Guilley, Naghmeh Karimi, Raphael Viera, Iyad Zaarour |
| 2026 | VTS | ROCKET: Runtime Operating-Condition Aware KEy Refreshing Technique for Resisting Side-Channel Analysis Attacks. | Hasin Ishraq Reefat, Hossein Pourmehrani, Jean-Luc Danger, Sylvain Guilley, Naghmeh Karimi |
| 2025 | DATE | Multi-Sensor Data Fusion for Enhanced Detection of Laser Fault Injection Attacks in Cryptographic Hardware: Practical Results. | Mohammad Ebrahimabadi, Raphael Viera, Sylvain Guilley, Jean-Luc Danger, Jean-Max Dutertre, Naghmeh Karimi |
| 2025 | ETS | BISSEL: Built-In Self Security via Embedded Sensors for Reproducible Side-Channel Leakage Assessment. | Md Toufiq Hasan Anik, Hasin Ishraq Reefat, Jean-Luc Danger, Sylvain Guilley, Naghmeh Karimi |
| 2025 | SECRYPT | TIGER: TrIaGing KEy Refreshing Frequency via Digital Sensors. | Md Toufiq Hasan Anik, Hasin Ishraq Reefat, Mohammad Ebrahimabadi, Javad Bahrami, Hossein Pourmehrani, Jean-Luc Danger, Sylvain Guilley, Naghmeh Karimi |
| 2024 | IOLTS | EM Fault Injection-Induced Clock Glitches: From Mechanism Analysis to Novel Sensor Design. | Roukoz Nabhan, Jean-Max Dutertre, Jean-Baptiste Rigaud, Jean-Luc Danger, Laurent Sauvage |
| 2023 | DATE | Highlighting Two EM Fault Models While Analyzing a Digital Sensor Limitations. | Roukoz Nabhan, Jean-Max Dutertre, Jean-Baptiste Rigaud, Jean-Luc Danger, Laurent Sauvage |
| 2023 | FDTC | A Tale of Two Models: Discussing the Timing and Sampling EM Fault Injection Models. | Roukoz Nabhan, Jean-Max Dutertre, Jean-Baptiste Rigaud, Jean-Luc Danger, Laurent Sauvage |
| 2023 | IWSEC | Reliability of Ring Oscillator PUFs with Reduced Helper Data. | Julien Bguinot, Wei Cheng, Jean-Luc Danger, Sylvain Guilley, Olivier Rioul, Ville Yli-Myry |
| 2023 | VTS | Special Session: Security Verification & Testing for SR-Latch TRNGs. | Javad Bahrami, Mohammad Ebrahimabadi, Jean-Luc Danger, Sylvain Guilley, Naghmeh Karimi |
| 2022 | AICCSA | CAN-BERT do it? Controller Area Network Intrusion Detection System based on BERT Language Model. | Natasha Alkhatib, Maria Mushtaq, Hadi Ghauch, Jean-Luc Danger |
| 2022 | DATE | Leakage Power Analysis in Different S-Box Masking Protection Schemes. | Javad Bahrami, Mohammad Ebrahimabadi, Jean-Luc Danger, Sylvain Guilley, Naghmeh Karimi |
| 2022 | SECRYPT | On the Practicality of Relying on Simulations in Different Abstraction Levels for Pre-silicon Side-Channel Analysis. | Javad Bahrami, Mohammad Ebrahimabadi, Sofiane Takarabt, Jean-Luc Danger, Sylvain Guilley, Naghmeh Karimi |
| 2021 | ACNS | Telepathic Headache: Mitigating Cache Side-Channel Attacks on Convolutional Neural Networks. | Herv Chabanne, Jean-Luc Danger, Linda Guiga, Ulrich Khne |
| 2021 | DATE | Making Obfuscated PUFs Secure Against Power Side-Channel Based Modeling Attacks. | Trevor Kroeger, Wei Cheng, Sylvain Guilley, Jean-Luc Danger, Naghmeh Karimi |
| 2021 | DSD | Analysis of a Laser-induced Instructions Replay Fault Model in a 32-bit Microcontroller. | Vanthanh Khuat, Jean-Max Dutertre, Jean-Luc Danger |
| 2021 | DSD | RSM Protection of the PRESENT Lightweight Cipher as a RISC-V Extension. | Etienne Tehrani, Tarik Graba, Abdelmalek Si-Merabet, Jean-Luc Danger |
| 2021 | FDTC | Laser Fault Injection in a 32-bit Microcontroller: from the Flash Interface to the Execution Pipeline. | Vanthanh Khuat, Jean-Luc Danger, Jean-Max Dutertre |
| 2021 | NCA | Water- PUF: An Insider Threat Resistant PUF Enrollment Protocol Based on Machine Learning Watermarking. | Sameh Khalfaoui, Jean Leneutre, Arthur Villard, Ivan Gazeau, Jingxuan Ma, Jean-Luc Danger, Pascal Urien |
| 2020 | DATE | Effect of Aging on PUF Modeling Attacks based on Power Side-Channel Observations. | Trevor Kroeger, Wei Cheng, Sylvain Guilley, Jean-Luc Danger, Naghmeh Karimi |
| 2020 | DSD | RISC-V Extension for Lightweight Cryptography. | Etienne Tehrani, Tarik Graba, Abdelmalek Si-Merabet, Jean-Luc Danger |
| 2020 | ETS | PUF Enrollment and Life Cycle Management: Solutions and Perspectives for the Test Community. | Amir Alipour, Vincent Beroulle, Bertrand Cambou, Jean-Luc Danger, Giorgio Di Natale, David Hly, Sylvain Guilley, Naghmeh Karimi |
| 2020 | ETS | Failure and Attack Detection by Digital Sensors. | Md Toufiq Hasan Anik, Rachit Saini, Jean-Luc Danger, Sylvain Guilley, Naghmeh Karimi |
| 2020 | FDTC | Single-bit Laser Fault Model in NOR Flash Memories: Analysis and Exploitation. | Alexandre Menu, Jean-Max Dutertre, Jean-Baptiste Rigaud, Brice Colombier, Pierre-Alain Mollic, Jean-Luc Danger |
| 2020 | ICCD | On-Chip Voltage and Temperature Digital Sensor for Security, Reliability, and Portability. | Md Toufiq Hasan Anik, Mohammad Ebrahimabadi, Hamed Pirsiavash, Jean-Luc Danger, Sylvain Guilley, Naghmeh Karimi |
| 2020 | ITC | Cross-PUF Attacks on Arbiter-PUFs through their Power Side-Channel. | Trevor Kroeger, Wei Cheng, Sylvain Guilley, Jean-Luc Danger, Naghmeh Karimi |
| 2020 | VLSID | On the Effect of Aging on Digital Sensors. | Md Toufiq Hasan Anik, Sylvain Guilley, Jean-Luc Danger, Naghmeh Karimi |
| 2019 | DSD | LAOCON: A Run-Time Monitoring and Verification Approach for Hardware Trojan Detection. | Jean-Luc Danger, Laurent Fribourg, Ulrich Khne, Maha Naceur |
| 2019 | FDTC | Precise Spatio-Temporal Electromagnetic Fault Injections on Data Transfers. | Alexandre Menu, Shivam Bhasin, Jean-Max Dutertre, Jean-Baptiste Rigaud, Jean-Luc Danger |
| 2018 | DSD | CCFI-Cache: A Transparent and Flexible Hardware Protection for Code and Control-Flow Integrity. | Jean-Luc Danger, Adrien Facon, Sylvain Guilley, Karine Heydemann, Ulrich Khne, Abdelmalek Si-Merabet, Michal Timbert |
| 2018 | DSD | Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology. | Jean-Luc Danger, Risa Yashiro, Tarik Graba, Yves Mathieu, Abdelmalek Si-Merabet, Kazuo Sakiyama, Noriyuki Miura, Makoto Nagata |
| 2018 | DSD | An Improved Analysis of Reliability and Entropy for Delay PUFs. | Alexander Schaub, Jean-Luc Danger, Sylvain Guilley, Olivier Rioul |
| 2018 | IOLTS | On the Effect of Aging in Detecting Hardware Trojan Horses with Template Analysis. | Naghmeh Karimi, Jean-Luc Danger, Sylvain Guilley |
| 2018 | WISTP | Prediction-Based Intrusion Detection System for In-Vehicle Networks Using Supervised Learning and Outlier-Detection. | Khaled Karray, Jean-Luc Danger, Sylvain Guilley, Moulay Abdelaziz Elaabid |
| 2018 | WISTP | Generic Architecture for Lightweight Block Ciphers: A First Step Towards Agile Implementation of Multiple Ciphers. | Etienne Tehrani, Jean-Luc Danger, Tarik Graba |
| 2017 | DATE | Analyzing security breaches of countermeasures throughout the refinement process in hardware design flow. | Jean-Luc Danger, Sylvain Guilley, Philippe Nguyen, Robert Nguyen, Youssef Souissi |
| 2017 | ETS | Impact of the switching activity on the aging of delay-PUFs. | Naghmeh Karimi, Jean-Luc Danger, Mariem Slimani, Sylvain Guilley |
| 2016 | CHES | Correlated Extra-Reductions Defeat Blinded Regular Exponentiation. | Margaux Dugardin, Sylvain Guilley, Jean-Luc Danger, Zakaria Najm, Olivier Rioul |
| 2016 | DAC | PLL to the rescue: a novel EM fault countermeasure. | Noriyuki Miura, Zakaria Najm, Wei He, Shivam Bhasin, Xuan Thuy Ngo, Makoto Nagata, Jean-Luc Danger |
| 2016 | ISIT | Inter-class vs. mutual information as side-channel distinguishers. | Olivier Rioul, Annelie Heuser, Sylvain Guilley, Jean-Luc Danger |
| 2016 | ISIT | On the entropy of Physically Unclonable Functions. | Olivier Rioul, Patrick Sol, Sylvain Guilley, Jean-Luc Danger |
| 2016 | TrustCom | Delay PUF Assessment Method Based on Side-Channel and Modeling Analyzes: The Final Piece of All-in-One Assessment Methodology. | Kazuhide Fukushima, Youssef Souissi, Seira Hidano, Robert Nguyen, Jean-Luc Danger, Sylvain Guilley, Yuto Nakano, Shinsaku Kiyomoto, Laurent Sauvage |
| 2015 | ASPDAC | A novel methodology for testing hardware security and trust exploiting On-Chip Power noise Measurement. | Daisuke Fujimoto, Makoto Nagata, Shivam Bhasin, Jean-Luc Danger |
| 2015 | DATE | Hardware trojan detection by delay and electromagnetic measurements. | Xuan Thuy Ngo, Ingrid Exurville, Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Zakaria Najm, Jean-Baptiste Rigaud, Bruno Robisson |
| 2015 | DSD | Integrated Sensor: A Backdoor for Hardware Trojan Insertions? | Xuan Thuy Ngo, Zakaria Najm, Shivam Bhasin, Debapriya Basu Roy, Jean-Luc Danger, Sylvain Guilley |
| 2015 | ICCD | From theory to practice of private circuit: A cautionary note. | Debapriya Basu Roy, Shivam Bhasin, Sylvain Guilley, Jean-Luc Danger, Debdeep Mukhopadhyay |
| 2014 | ACSAC | HCODE: Hardware-Enhanced Real-Time CFI. | Jean-Luc Danger, Sylvain Guilley, Thibault Porteboeuf, Florian Praden, Michal Timbert |
| 2014 | CASES | Encoding the state of integrated circuits: a proactive and reactive protection against hardware Trojans horses. | Xuan Thuy Ngo, Sylvain Guilley, Shivam Bhasin, Jean-Luc Danger, Zakaria Najm |
| 2014 | DATE | Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation Methodology. | Shivam Bhasin, Jean-Luc Danger, Tarik Graba, Yves Mathieu, Daisuke Fujimoto, Makoto Nagata |
| 2014 | DATE | Hacking and protecting IC hardware. | Said Hamdioui, Jean-Luc Danger, Giorgio Di Natale, Fethulah Smailbegovic, Gerard van Battum, Mark Tehranipoor |
| 2014 | FPL | Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security. | Emna Amouri, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, Habib Mehrez |
| 2014 | ISCA | Side-channel leakage and trace compression using normalized inter-class variance. | Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Zakaria Najm |
| 2014 | ISCA | Side channel analysis on an embedded hardware fingerprint biometric comparator & low cost countermeasures. | Taoufik Chouta, Tarik Graba, Jean-Luc Danger, Julien Bringer, Mal Berthier, Yves Bocktaels, Mlanie Favre, Herv Chabanne |
| 2014 | POPL | Hardware-enforced Protection against Software Reverse-Engineering based on an Instruction Set Encoding. | Jean-Luc Danger, Sylvain Guilley, Florian Praden |
| 2014 | WISTP | A Pre-processing Composition for Secret Key Recovery on Android Smartphone. | Yuto Nakano, Youssef Souissi, Robert Nguyen, Laurent Sauvage, Jean-Luc Danger, Sylvain Guilley, Shinsaku Kiyomoto, Yutaka Miyake |
| 2013 | CARDIS | Time-Frequency Analysis for Second-Order Attacks. | Pierre Belgarric, Shivam Bhasin, Nicolas Bruneau, Jean-Luc Danger, Nicolas Debande, Sylvain Guilley, Annelie Heuser, Zakaria Najm, Olivier Rioul |
| 2013 | CASES | A low-entropy first-degree secure provable masking scheme for resource-constrained devices. | Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Zakaria Najm |
| 2013 | DSD | FPGA Design of an Open-Loop True Random Number Generator. | Florent Lozach, Molka Ben-Romdhane, Tarik Graba, Jean-Luc Danger |
| 2013 | FDTC | Hardware Trojan Horses in Cryptographic IP Cores. | Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Xuan Thuy Ngo, Laurent Sauvage |
| 2013 | ISCA | Evaluation of delay PUFs on CMOS 65 nm technology: ASIC vs FPGA. | Zouha Cherif, Jean-Luc Danger, Florent Lozach, Yves Mathieu, Lilian Bossuet |
| 2013 | ISIT | Multiply constant weight codes. | Zouha Cherif, Jean-Luc Danger, Sylvain Guilley, Jon-Lark Kim, Patrick Sol |
| 2012 | CARDIS | Low-Cost Countermeasure against RPA. | Jean-Luc Danger, Sylvain Guilley, Philippe Hoogvorst, Cdric Murdica, David Naccache |
| 2012 | CHES | 3D Hardware Canaries. | Sbastien Briais, Stphane Caron, Jean-Michel Cioranesco, Jean-Luc Danger, Sylvain Guilley, Jacques-Henri Jourdan, Arthur Milchior, David Naccache, Thibault Porteboeuf |
| 2012 | DATE | RSM: A small and fast countermeasure for AES, secure against 1st and 2nd-order zero-offset SCAs. | Maxime Nassar, Youssef Souissi, Sylvain Guilley, Jean-Luc Danger |
| 2012 | DSD | An Easy-to-Design PUF Based on a Single Oscillator: The Loop PUF. | Zouha Cherif, Jean-Luc Danger, Sylvain Guilley, Lilian Bossuet |
| 2012 | DSD | A Small and High-Performance Coprocessor for Fingerprint Match-on-Card. | Taoufik Chouta, Jean-Luc Danger, Laurent Sauvage, Tarik Graba |
| 2012 | FDTC | Random Active Shield. | Sbastien Briais, Jean-Michel Cioranesco, Jean-Luc Danger, Sylvain Guilley, David Naccache, Thibault Porteboeuf |
| 2012 | ICICS | Comparison between Side-Channel Analysis Distinguishers. | Houssem Maghrebi, Olivier Rioul, Sylvain Guilley, Jean-Luc Danger |
| 2012 | INDOCRYPT | Leakage Squeezing of Order Two. | Claude Carlet, Jean-Luc Danger, Sylvain Guilley, Houssem Maghrebi |
| 2012 | MICRO | From Cryptography to Hardware: Analyzing Embedded Xilinx BRAM for Cryptographic Applications. | Shivam Bhasin, Sylvain Guilley, Jean-Luc Danger |
| 2012 | MICRO | Wavelet transform based pre-processing for side channel analysis. | Nicolas Debande, Youssef Souissi, M. Abdelaziz Elaabid, Sylvain Guilley, Jean-Luc Danger |
| 2012 | WISTP | On the Optimality of Correlation Power Attack on Embedded Cryptographic Systems. | Youssef Souissi, Nicolas Debande, Sami Mekki, Sylvain Guilley, Ali Maalaoui, Jean-Luc Danger |
| 2011 | DATE | Enhancement of simple electro-magnetic attacks by pre-characterization in frequency domain and demodulation techniques. | Olivier Meynard, Denis Ral, Florent Flament, Sylvain Guilley, Naofumi Homma, Jean-Luc Danger |
| 2011 | ETFA | Non intrusive fault detection through electromagnetism analysis. | Sbastien Thomas, Didier Regis, David Faura, Marc Gatti, Guillaume Duc, Jean-Luc Danger |
| 2011 | INDOCRYPT | Formal Analysis of the Entropy / Security Trade-off in First-Order Masking Countermeasures against Side-Channel Attacks. | Maxime Nassar, Sylvain Guilley, Jean-Luc Danger |
| 2011 | WISTP | Formal Framework for the Evaluation of Waveform Resynchronization Algorithms. | Sylvain Guilley, Karim Khalfallah, Victor Lomn, Jean-Luc Danger |
| 2011 | WISTP | Leakage Squeezing Countermeasure against High-Order Attacks. | Houssem Maghrebi, Sylvain Guilley, Jean-Luc Danger |
| 2010 | CASES | Countering early evaluation: an approach towards robust dual-rail precharge logic. | Shivam Bhasin, Sylvain Guilley, Florent Flament, Nidhal Selmane, Jean-Luc Danger |
| 2010 | DATE | Far Correlation-based EMA with a precharacterized leakage model. | Olivier Meynard, Sylvain Guilley, Jean-Luc Danger, Laurent Sauvage |
| 2010 | DATE | BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluation. | Maxime Nassar, Shivam Bhasin, Jean-Luc Danger, Guillaume Duc, Sylvain Guilley |
| 2010 | FDTC | Fault Injection Resilience. | Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane |
| 2010 | ICASSP | Improvement of power analysis attacks using Kalman filter. | Youssef Souissi, Sylvain Guilley, Jean-Luc Danger, Sami Mekki, Guillaume Duc |
| 2010 | ICISC | First Principal Components Analysis: A New Side Channel Distinguisher. | Youssef Souissi, Maxime Nassar, Sylvain Guilley, Jean-Luc Danger, Florent Flament |
| 2010 | WISA | Combined Side-Channel Attacks. | M. Abdelaziz Elaabid, Olivier Meynard, Sylvain Guilley, Jean-Luc Danger |
| 2009 | DATE | Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints. | Laurent Sauvage, Sylvain Guilley, Jean-Luc Danger, Yves Mathieu, Maxime Nassar |
| 2009 | FDTC | WDDL is Protected against Setup Time Violation Attacks. | Nidhal Selmane, Shivam Bhasin, Sylvain Guilley, Tarik Graba, Jean-Luc Danger |
| 2008 | DAC | An 8x8 run-time reconfigurable FPGA embedded in a SoC. | Sumanta Chaudhuri, Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Jean-Luc Danger |
| 2008 | EDCC | Practical Setup Time Violation Attacks on AES. | Nidhal Selmane, Sylvain Guilley, Jean-Luc Danger |
| 2008 | FDTC | Silicon-level Solutions to Counteract Passive and Active Attacks. | Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane, Renaud Pacalet |
| 2008 | FPGA | Efficient tiling patterns for reconfigurable gate arrays. | Sumanta Chaudhuri, Jean-Luc Danger, Philippe Hoogvorst, Sylvain Guilley |
| 2008 | FPL | Area optimization of cryptographic co-processors implemented in dual-rail with precharge positive logic. | Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Philippe Hoogvorst |
| 2008 | VTC | Probabilistic Equalizer for Ultra-Wideband Energy Detection. | Sami Mekki, Jean-Luc Danger, Benoit Miscopein, Jean Schwoerer, Joseph Jean Boutros |
| 2007 | FPL | Efficient Modeling and Floorplanning of Embedded-FPGA Fabric. | Sumanta Chaudhuri, Jean-Luc Danger, Sylvain Guilley |
| 2005 | PIMRC | Reconfigurable Implementation Issues of a Detection Scheme for DS-CDMA High Data Rate Connections. | Ioannis Krikidis, Jean-Luc Danger, Lirida A. B. Naviner |
| 2004 | WCNC | A finger configuration algorithm for a reconfigurable Rake receiver. | Ioannis Krikidis, Jean-Luc Danger, Lirida A. B. Naviner |
| 2000 | FPGA | Low power digital design in FPGAs (poster abstract): a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption. | Andrs D. Garca, Jean-Luc Danger, Wayne P. Burleson |
| 2000 | ISCAS | Low power digital design in FPGAs: a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption. | Andrs D. Garca, Wayne P. Burleson, Jean-Luc Danger |
| 1999 | FPGA | High-Performance Low-Cost Implementation of Two-Dimensional DCT Processor nn FPGA. | Lirida A. B. Naviner, Jean-Luc Danger, C. Laurent |
| 1999 | FPL | Power Modelling in Field Programmable Gate Arrays (FPGA). | Andrs D. Garca, Wayne P. Burleson, Jean-Luc Danger |