| 2026 | ASPDAC | Boosting Scalability and Performance: Macro Placement for Flexible 3D-Stacked ML Accelerators. | Jiawei Hu, Canlin Zhang, Pruek Vanna-Iampikul, Tushar Krishna, Sung Kyu Lim |
| 2026 | ASPDAC | Differentiable Tier Assignment for Timing and Congestion-Aware Routing in 3D ICs. | Yuan-Hsiang Lu, Hao-Hsiang Hsiao, Yi-Chen Lu, Haoxing Ren, Sung Kyu Lim |
| 2026 | ASPDAC | Graph Attention-Based Current Crowding Analysis at TSV Interfaces in 3D Power Delivery Networks. | Zheng Yang, Zhen Zhuang, Tsung-Yi Ho, Sung Kyu Lim |
| 2026 | ASPDAC | DPO-3D: Differentiable Power Delivery Network Optimization via Flexible Modeling for Routability and IR-Drop Tradeoff in Face-to-Face 3D ICs. | Zhen Zhuang, Zheng Yang, Yuxuan Zhao, Jiawei Hu, Bei Yu, Sung Kyu Lim, Tsung-Yi Ho |
| 2025 | DAC | InsightAlign: A Transferable Physical Design Recipe Recommender Based on Design Insights. | Hao-Hsiang Hsiao, Sudipto Kundu, Wei Zeng, Wei-Ting Chan, Deyuan Guo, Sung Kyu Lim |
| 2025 | DAC | DCO-3D: Differentiable Congestion Optimization in 3D ICs. | Hao-Hsiang Hsiao, Yi-Chen Lu, Pruek Vanna-Iampikul, Anthony Agnesina, Rongjian Liang, Yuan-Hsiang Lu, Haoxing Ren, Sung Kyu Lim |
| 2025 | DAC | GNN-MLS: Signal Routing in Mixed-Node 3D ICs through GNN-Assisted Metal Layer Sharing. | Jiawei Hu, Pruek Vanna-Iampikul, Zhen Zhuang, Tsung-Yi Ho, Sung Kyu Lim |
| 2025 | DAC | A Systematic Approach for Multi-objective Double-side Clock Tree Synthesis. | Xun Jiang, Haoran Lu, Yuxuan Zhao, Jiarui Wang, Zizheng Guo, Heng Wu, Bei Yu, Sung Kyu Lim, Runsheng Wang, Ru Huang, Yibo Lin |
| 2025 | DAC | BS-PDN-Last: Towards Optimal Power Delivery Network Design With Multifunctional Backside Metal Layers. | Min Gyu Park, Amaan Rahman, Sung Kyu Lim |
| 2025 | ICCAD | BUFFALO: PPA-Configurable, LLM-based Buffer Tree Generation via Group Relative Policy Optimization. | Hao-Hsiang Hsiao, Yi-Chen Lu, Sung Kyu Lim, Haoxing Ren |
| 2025 | ICCAD | Snake-3D: Differentiable Learning for Cross-Tier Logic Path Snaking Optimization in 3D ICs. | Yen-Hsiang Huang, Sung Kyu Lim |
| 2025 | ICCAD | Closing the Gap: Advantages of Block-Level over Gate-Level in 3D IC Design for Advanced Nodes. | Min Gyu Park, Pruek Vanna-Iampikul, Sung Kyu Lim |
| 2025 | ICCAD | 3D Acceleration for Mixture-of-Experts and Multi-Head Attention Spiking Transformers with Dynamic Head Pruning. | Boxun Xu, Junyoung Hwang, Pruek Vanna-Iampikul, Yuxuan Yin, Sung Kyu Lim, Peng Li |
| 2025 | ISLPED | MIX-3D: AI-based Architecture-Circuit Co-design Methodology for Mixed-Node, Mixed-Area 3D ICs. | Min Gyu Park, Doyun Kim, Sung Kyu Lim |
| 2025 | ISLPED | On-chip Integrated Voltage Regulators: Frontside, Backside, or Off-Chipƒ. | Amaan Rahman, Seungmin Woo, Zheng Yang, Sung Kyu Lim |
| 2024 | DAC | GNN-assisted Back-side Clock Routing Methodology for Advance Technologies. | Nesara Eranna Bethur, Pruek Vanna-Iampikul, Odysseas Zografos, Lingjun Zhu, Giuliano Sisto, Dragomir Milojevic, Alberto Garca Ortiz, Geert Hellings, Julien Ryckaert, Francky Catthoor, Sung Kyu Lim |
| 2024 | DAC | ML-based Physical Design Parameter Optimization for 3D ICs: From Parameter Selection to Optimization. | Hao-Hsiang Hsiao, Pruek Vanna-Iampikul, Yi-Chen Lu, Sung Kyu Lim |
| 2024 | ICCAD | Multi-Tier 3D SRAM Module Design: Targeting Bit-Line and Word-Line Folding. | Aditya Sridharan Iyer, Daehyun Kim, Saibal Mukhopadhyay, Sung Kyu Lim |
| 2024 | ICCAD | AI-Driven Evaluation and Optimization of Bump Pitch Effects on Chiplet and Interposer Design Quality. | Seungmin Woo, Pruek Vanna-Iampikul, Sung Kyu Lim |
| 2024 | ICCAD | Spiking Transformer Hardware Accelerators in 3D Integration. | Boxun Xu, Junyoung Hwang, Pruek Vanna-Iampikul, Sung Kyu Lim, Peng Li |
| 2024 | ISLPED | Hetero-3D: Maximizing Performance and Power Delivery Benefits of Heterogeneous 3D ICs. | Lingjun Zhu, Jiawei Hu, Gauthaman Murali, Sung Kyu Lim |
| 2023 | DAC | RL-CCD: Concurrent Clock and Data Optimization using Attention-Based Self-Supervised Reinforcement Learning. | Yi-Chen Lu, Wei-Ting Chan, Deyuan Guo, Sudipto Kundu, Vishal Khandelwal, Sung Kyu Lim |
| 2023 | DAC | Glass Interposer Integration of Logic and Memory Chiplets: PPA and Power/Signal Integrity Benefits. | Pruek Vanna-Iampikul, Lingjun Zhu, Serhat Erdogan, Mohanalingam Kathaperumal, Ravi Agarwal, Ram Gupta, Kevin Rinebold, Sung Kyu Lim |
| 2023 | DAC | INVITED: Design Automation Needs for Monolithic 3D ICs: Accomplishments and Gaps. | Lingjun Zhu, Sung Kyu Lim |
| 2023 | DATE | Ultra-Dense 3D Physical Design Unlocks New Architectural Design Points with Large Benefits. | Tathagata Srimani, Robert M. Radway, Jinwoo Kim, Kartik Prabhu, Dennis Rich, Carlo Gilardi, Priyanka Raina, Max M. Shulaker, Sung Kyu Lim, Subhasish Mitra |
| 2023 | DATE | Securing Heterogeneous 2.5D ICs Against IP Theft through Dynamic Interposer Obfuscation. | Jonti Talukdar, Arjun Chaudhuri, Jinwoo Kim, Sung Kyu Lim, Krishnendu Chakrabarty |
| 2023 | ICCAD | 3DNN-Xplorer: A Machine Learning Framework for Design Space Exploration of Heterogeneous 3D DNN Accelerators. | Gauthaman Murali, Aditya Iyer, Navneeth Ravichandran, Sung Kyu Lim |
| 2023 | ISCAS | A 3D Implementation of Convolutional Neural Network for Fast Inference. | Narasinga Rao Miniskar, Pruek Vanna-Iampikul, Aaron R. Young, Sung Kyu Lim, Frank Liu, Jieun Yoo, Corrinne Mills, Nhan Tran, Farah Fahim, Jeffrey S. Vetter |
| 2023 | ISLPED | A Comparative Study on Front-Side, Buried and Back-Side Power Rail Topologies in 3nm Technology Node. | Sandra Maria Shaji, Lingjun Zhu, Jun-Sik Yoon, Sung Kyu Lim |
| 2022 | DATE | MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration. | Matheus A. Cavalcante, Anthony Agnesina, Samuel Riedel, Moritz Brunion, Alberto Garca-Ortiz, Dragomir Milojevic, Francky Catthoor, Sung Kyu Lim, Luca Benini |
| 2022 | ICCAD | On Advancing Physical Design Using Graph Neural Networks. | Yi-Chen Lu, Sung Kyu Lim |
| 2022 | ISLPED | Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs. | Anthony Agnesina, Moritz Brunion, Alberto Garca Ortiz, Francky Catthoor, Dragomir Milojevic, Manu Komalan, Matheus A. Cavalcante, Samuel Riedel, Luca Benini, Sung Kyu Lim |
| 2022 | ISLPED | 3D IC Tier Partitioning of Memory Macros: PPA vs. Thermal Tradeoffs. | Lingjun Zhu, Nesara Eranna Bethur, Yi-Chen Lu, Youngsang Cho, Yunhyeok Im, Sung Kyu Lim |
| 2021 | DAC | Micro-bumping, Hybrid Bonding, or Monolithic? A PPA Study for Heterogeneous 3D IC Options. | Jinwoo Kim, Lingjun Zhu, Hakki Mert Torun, Madhavan Swaminathan, Sung Kyu Lim |
| 2021 | DAC | RL-Sizer: VLSI Gate Sizing for Timing Optimization using Deep Reinforcement Learning. | Yi-Chen Lu, Siddhartha Nath, Vishal Khandelwal, Sung Kyu Lim |
| 2021 | DAC | Heterogeneous Monolithic 3D ICs: EDA Solutions, and Power, Performance, Cost Tradeoffs. | Sai Surya Kiran Pentapati, Sung Kyu Lim |
| 2021 | DATE | Heterogeneous 3D ICs: Current Status and Future Directions for Physical Design Technologies. | Gauthaman Murali, Sung Kyu Lim |
| 2021 | HPCA | FAFNIR: Accelerating Sparse Gathering by Using Efficient Near-Memory Intelligent Reduction. | Bahar Asgari, Ramyad Hadidi, Jiashen Cao, Da Eun Shim, Sung Kyu Lim, Hyesoon Kim |
| 2021 | ICCAD | ParaMitE: Mitigating Parasitic CNFETs in the Presence of Unetched CNTs. | Sanmitra Banerjee, Arjun Chaudhuri, Jinwoo Kim, Gauthaman Murali, Mark Nelson, Sung Kyu Lim, Krishnendu Chakrabarty |
| 2021 | ICCAD | Security Closure of Physical Layouts ICCAD Special Session Paper. | Johann Knechtel, Jayanth Gopinath, Jitendra Bhandari, Mohammed Ashraf, Hussam Amrouch, Shekhar Borkar, Sung Kyu Lim, Ozgur Sinanoglu, Ramesh Karri |
| 2021 | ICCAD | Doomed Run Prediction in Physical Design by Exploiting Sequential Flow and Graph Learning. | Yi-Chen Lu, Siddhartha Nath, Vishal Khandelwal, Sung Kyu Lim |
| 2021 | ISLPED | Power, Performance, Area and Cost Analysis of Memory-on-Logic Face-to-Face Bonded 3D Processor Designs. | Anthony Agnesina, Moritz Brunion, Jinwoo Kim, Alberto Garca Ortiz, Dragomir Milojevic, Francky Catthoor, Manu Perumkunnil, Sung Kyu Lim |
| 2021 | ISLPED | Power Delivery and Thermal-Aware Arm-Based Multi-Tier 3D Architecture. | Lingjun Zhu, Tuan Ta, Rossana Liu, Rahul Mathur, Xiaoqing Xu, Shidhartha Das, Ankit Kaul, Alejandro Rico, Doug Joseph, Brian Cline, Sung Kyu Lim |
| 2020 | DAC | TP-GNN: A Graph Neural Network Framework for Tier Partitioning in Monolithic 3D ICs. | Yi-Chen Lu, Sai Surya Kiran Pentapati, Lingjun Zhu, Kambiz Samadi, Sung Kyu Lim |
| 2020 | DATE | Macro-3D: A Physical Design Methodology for Face-to-Face-Stacked Heterogeneous 3D ICs. | Lennart Bamberg, Alberto Garca Ortiz, Lingjun Zhu, Sai Pentapati, Da Eun Shim, Sung Kyu Lim |
| 2020 | ICCAD | VLSI Placement Parameter Optimization using Deep Reinforcement Learning. | Anthony Agnesina, Kyungwook Chang, Sung Kyu Lim |
| 2020 | ICCAD | RTL-to-GDS Design Tools for Monolithic 3D ICs. | Jinwoo Kim, Gauthaman Murali, Pruek Vanna-Iampikul, Edward Lee, Daehyun Kim, Arjun Chaudhuri, Sanmitra Banerjee, Krishnendu Chakrabarty, Saibal Mukhopadhyay, Sung Kyu Lim |
| 2020 | ICCAD | A Fast Learning-Driven Signoff Power Optimization Framework. | Yi-Chen Lu, Siddhartha Nath, Sai Surya Kiran Pentapati, Sung Kyu Lim |
| 2020 | ICCAD | Pin-3D: A Physical Synthesis and Post-Layout Optimization Flow for Heterogeneous Monolithic 3D ICs. | Sai Surya Kiran Pentapati, Kyungwook Chang, Vassilios Gerousis, Rwik Sengupta, Sung Kyu Lim |
| 2020 | ICCD | A Fault-Tolerant and High-Speed Memory Controller Targeting 3D Flash Memory Cubes for Space Applications. | Anthony Agnesina, Da Eun Shim, James Yamaguchi, Christian Krutzik, John Carson, Dan Nakamura, Sung Kyu Lim |
| 2020 | ICCD | Silicon vs. Organic Interposer: PPA and Reliability Tradeoffs in Heterogeneous 2.5D Chiplet Integration. | Jinwoo Kim, Venkata Chaitanya Krishna Chekuri, Nael Mizanur Rahman, Majid Ahadi Dolatsara, Hakki Mert Torun, Madhavan Swaminathan, Saibal Mukhopadhyay, Sung Kyu Lim |
| 2020 | ISLPED | Pin-in-the-middle: an efficient block pin assignment methodology for block-level monolithic 3D ICs. | Bon Woong Ku, Sung Kyu Lim |
| 2019 | DAC | Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse. | Jinwoo Kim, Gauthaman Murali, Heechun Park, Eric Qin, Hyoukjun Kwon, Venkata Chaitanya Krishna Chekuri, Nihar Dasari, Arvind Singh, Minah Lee, Hakki Mert Torun, Kallol Roy, Madhavan Swaminathan, Saibal Mukhopadhyay, Tushar Krishna, Sung Kyu Lim |
| 2019 | DAC | RTL-to-GDS Tool Flow and Design-for-Test Solutions for Monolithic 3D ICs. | Heechun Park, Kyungwook Chang, Bon Woong Ku, Jinwoo Kim, Edward Lee, Daehyun Kim, Arjun Chaudhuri, Sanmitra Banerjee, Saibal Mukhopadhyay, Krishnendu Chakrabarty, Sung Kyu Lim |
| 2019 | ETS | Built-in Self-Test for Inter-Layer Vias in Monolithic 3D ICs. | Arjun Chaudhuri, Sanmitra Banerjee, Heechun Park, Bon Woong Ku, Krishnendu Chakrabarty, Sung Kyu Lim |
| 2019 | ICCAD | Reducing Compilation Effort in Commercial FPGA Emulation Systems Using Machine Learning. | Anthony Agnesina, Etienne Lepercq, Jose Escobedo, Sung Kyu Lim |
| 2019 | ICCAD | GAN-CTS: A Generative Adversarial Framework for Clock Tree Prediction and Optimization. | Yi-Chen Lu, Jeehyun Lee, Anthony Agnesina, Kambiz Samadi, Sung Kyu Lim |
| 2019 | ICCAD | A Spectral Convolutional Net for Co-Optimization of Integrated Voltage Regulators and Embedded Inductors. | Hakki Mert Torun, Huan Yu, Nihar Dasari, Venkata Chaitanya Krishna Chekuri, Arvind Singh, Jinwoo Kim, Sung Kyu Lim, Saibal Mukhopadhyay, Madhavan Swaminathan |
| 2019 | ISLPED | Tier Partitioning and Flip-flop Relocation Methods for Clock Trees in Monolithic 3D ICs. | Da Eun Shim, Sai Pentapati, Jeehyun Lee, Yun Seop Yu, Sung Kyu Lim |
| 2018 | DAC | A novel 3D DRAM memory cube architecture for space applications. | Anthony Agnesina, Amanvir Sidana, James Yamaguchi, Christian Krutzik, John Carson, Jean Yang-Scharlotta, Sung Kyu Lim |
| 2018 | DAC | Design and architectural co-optimization of monolithic 3D liquid state machine-based neuromorphic processor. | Bon Woong Ku, Yu Liu, Yingyezhe Jin, Sandeep Kumar Samal, Peng Li, Sung Kyu Lim |
| 2018 | DATE | In-growth test for monolithic 3D integrated SRAM. | Pu Pang, Yixun Zhang, Tianjian Li, Sung Kyu Lim, Quan Chen, Xiaoyao Liang, Li Jiang |
| 2018 | ICCAD | Area-efficient and low-power face-to-face-bonded 3D liquid state machine design. | Bon Woong Ku, Yu Liu, Yingyezhe Jin, Peng Li, Sung Kyu Lim |
| 2018 | ISLPED | Road to High-Performance 3D ICs: Performance Optimization Methodologies for Monolithic 3D ICs. | Kyungwook Chang, Sai Pentapati, Da Eun Shim, Sung Kyu Lim |
| 2017 | ICCAD | Design automation and testing of monolithic 3D ICs: Opportunities, challenges, and solutions: (Invited paper). | Kyungwook Chang, Abhishek Koneru, Krishnendu Chakrabarty, Sung Kyu Lim |
| 2017 | ICCAD | Full-chip monolithic 3D IC design and power performance analysis with ASAP7 library: (Invited Paper). | Kyungwook Chang, Bon Woong Ku, Saurabh Sinha, Sung Kyu Lim |
| 2017 | ISLPED | Frequency and time domain analysis of power delivery network for monolithic 3D ICs. | Kyungwook Chang, Shidhartha Das, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim |
| 2017 | ISLPED | Monolithic 3D IC designs for low-power deep neural networks targeting speech recognition. | Kyungwook Chang, Deepak Kadetotad, Yu Cao, Jae-sun Seo, Sung Kyu Lim |
| 2017 | ISLPED | Transistor-level monolithic 3D standard cell layout optimization for full-chip static power integrity. | Bon Woong Ku, Taigon Song, Arthur Nieuwoudt, Sung Kyu Lim |
| 2017 | ISLPED | Full chip power benefits with negative capacitance FETs. | Sandeep Kumar Samal, Sourabh Khandelwal, Asif Islam Khan, Sayeef S. Salahuddin, Chenming Hu, Sung Kyu Lim |
| 2016 | DAC | Match-making for monolithic 3D IC: finding the right technology node. | Kyungwook Chang, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim |
| 2016 | ICCAD | Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools. | Kyungwook Chang, Saurabh Sinha, Brian Cline, Raney Southerland, Michael Doherty, Greg Yeric, Sung Kyu Lim |
| 2016 | ICCAD | How much cost reduction justifies the adoption of monolithic 3D ICs at 7nm node? | Bon Woong Ku, Peter Debacker, Dragomir Milojevic, Praveen Raghavan, Sung Kyu Lim |
| 2016 | ICCAD | Tier partitioning strategy to mitigate BEOL degradation and cost issues in monolithic 3D ICs. | Sandeep Kumar Samal, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna, Sung Kyu Lim |
| 2016 | ISLPED | Four-tier Monolithic 3D ICs: Tier Partitioning Methodology and Power Benefit Study. | Kwang Min Kim, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim |
| 2016 | ISLPED | Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs. | Bon Woong Ku, Peter Debacker, Dragomir Milojevic, Praveen Raghavan, Diederik Verkest, Aaron Thean, Sung Kyu Lim |
| 2016 | ISLPED | How to Cope with Slow Transistors in the Top-tier of Monolithic 3D ICs: Design Studies and CAD Solutions. | Sandeep Kumar Samal, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna, Sung Kyu Lim |
| 2015 | DAC | Tier-partitioning for power delivery vs cooling tradeoff in 3D VLSI for mobile applications. | Shreepad Panth, Kambiz Samadi, Yang Du, Sung Kyu Lim |
| 2015 | DAC | Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM. | Yarui Peng, Bon Woong Ku, Youn-Sik Park, Kwang-Il Park, Seong-Jin Jang, Joo-Sun Choi, Sung Kyu Lim |
| 2015 | ICCAD | Full-chip Inter-die Parasitic Extraction in Face-to-Face-Bonded 3D ICs. | Yarui Peng, Taigon Song, Dusan Petranovic, Sung Kyu Lim |
| 2015 | ICCAD | Three-Tier 3D ICs for More Power Reduction: Strategies in CAD, Design, and Bonding Selection. | Taigon Song, Shreepad Panth, Yoo-Jin Chae, Sung Kyu Lim |
| 2015 | ICCAD | A Novel Entropy Production Based Full-Chip TSV Fatigue Analysis. | Tianchen Wang, Sandeep Kumar Samal, Sung Kyu Lim, Yiyu Shi |
| 2015 | ISCAS | Stacking integration methodologies in 3D IC for 3D ultrasound image processing application: A stochastic flash ADC design case study. | Hourieh Attarzadeh, Sung Kyu Lim, Trond Ytterdal |
| 2015 | ISLPED | Power benefit study of monolithic 3D IC at the 7nm technology node. | Kyungwook Chang, Kartik Acharya, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim |
| 2015 | ITC | On diagnosable and tunable 3D clock network design for lifetime reliability enhancement. | Li Jiang, Pu Pang, Naifeng Jing, Sung Kyu Lim, Xiaoyao Liang, Qiang Xu |
| 2014 | DAC | On Enhancing Power Benefits in 3D ICs: Block Folding and Bonding Styles Perspective. | Moongon Jung, Taigon Song, Yang Wan, Yarui Peng, Sung Kyu Lim |
| 2014 | DAC | Power-Performance Study of Block-Level Monolithic 3D-ICs Considering Inter-Tier Performance Variations. | Shreepad Panth, Kambiz Samadi, Yang Du, Sung Kyu Lim |
| 2014 | DAC | Fast and Accurate Full-chip Extraction and Optimization of TSV-to-Wire Coupling. | Yarui Peng, Dusan Petranovic, Sung Kyu Lim |
| 2014 | DAC | Fast and Accurate Thermal Modeling and Optimization for Monolithic 3D ICs. | Sandeep Kumar Samal, Shreepad Panth, Kambiz Samadi, Mehdi Saedi, Yang Du, Sung Kyu Lim |
| 2014 | DATE | On GPU bus power reduction with 3D IC technologies. | Young-Joon Lee, Sung Kyu Lim |
| 2014 | ICCAD | Full chip impact study of power delivery network designs in monolithic 3D ICs. | Sandeep Kumar Samal, Kambiz Samadi, Pratyush Kamal, Yang Du, Sung Kyu Lim |
| 2014 | ISLPED | Design and CAD methodologies for low power gate-level monolithic 3D ICs. | Shreepad A. Panth, Kambiz Samadi, Yang Du, Sung Kyu Lim |
| 2013 | ASPDAC | Block-level designs of die-to-wafer bonded 3D ICs and their design quality tradeoffs. | Krit Athikulwongse, Dae Hyun Kim, Moongon Jung, Sung Kyu Lim |
| 2013 | ASPDAC | High-density integration of functional modules using monolithic 3D-IC technology. | Shreepad Panth, Kambiz Samadi, Yang Du, Sung Kyu Lim |
| 2013 | ASPDAC | Thermal-reliable 3D clock-tree synthesis considering nonlinear electrical-thermal-coupled TSV model. | Yang Shang, Chun Zhang, Hao Yu, Chuan Seng Tan, Xin Zhao, Sung Kyu Lim |
| 2013 | DAC | Power benefit study for ultra-high density transistor-level monolithic 3D ICs. | Young-Joon Lee, Daniel B. Limbrick, Sung Kyu Lim |
| 2013 | DAC | Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs. | Taigon Song, Chang Liu, Yarui Peng, Sung Kyu Lim |
| 2013 | ICCAD | Electromigration study for multi-scale power/ground vias in TSV-based 3D ICs. | Jiwoo Pak, Sung Kyu Lim, David Z. Pan |
| 2013 | ICCAD | On accurate full-chip extraction and optimization of TSV-to-TSV coupling elements in 3D ICs. | Yarui Peng, Taigon Song, Dusan Petranovic, Sung Kyu Lim |
| 2013 | ICCAD | Novel crack sensor for TSV-based 3D integrated circuits: design and deployment perspectives. | Chun Zhang, Moongon Jung, Sung Kyu Lim, Yiyu Shi |
| 2013 | ICCAD | Transient modeling of TSV-wire electromigration and lifetime analysis of power distribution network for 3D ICs. | Xin Zhao, Yang Wan, Michael Scheuermann, Sung Kyu Lim |
| 2013 | ISLPED | Design and analysis of 3D IC-based low power stereo matching processors. | Seung-Ho Ok, Kyeong-Ryeol Bae, Sung Kyu Lim, Byungin Moon |
| 2013 | ISLPED | Design and analysis of ultra low power processors using sub/near-threshold 3D stacked ICs. | Sandeep Kumar Samal, Yarui Peng, Yang Zhang, Sung Kyu Lim |
| 2012 | ASPDAC | Block-level 3D IC design with through-silicon-via planning. | Dae Hyun Kim, Rasit Onur Topaloglu, Sung Kyu Lim |
| 2012 | ASPDAC | Design for manufacturability and reliability for TSV-based 3D ICs. | David Z. Pan, Sung Kyu Lim, Krit Athikulwongse, Moongon Jung, Joydeep Mitra, Jiwoo Pak, Mohit Pathak, Jae-Seok Yang |
| 2012 | ASPDAC | Through-silicon-via-induced obstacle-aware clock tree synthesis for 3D ICs. | Xin Zhao, Sung Kyu Lim |
| 2012 | DAC | Exploiting die-to-die thermal coupling in 3D IC placement. | Krit Athikulwongse, Mohit Pathak, Sung Kyu Lim |
| 2012 | DAC | Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs. | Moongon Jung, David Z. Pan, Sung Kyu Lim |
| 2012 | DAC | Analysis of DC current crowding in through-silicon-vias and its impact on power integrity in 3D ICs. | Xin Zhao, Michael Scheuermann, Sung Kyu Lim |
| 2012 | ICCAD | Ultra high density logic designs using transistor-level monolithic 3D integration. | Young-Joon Lee, Patrick Morrow, Sung Kyu Lim |
| 2012 | ICCAD | Electromigration-aware routing for 3D ICs with stress-aware EM modeling. | Jiwoo Pak, Sung Kyu Lim, David Z. Pan |
| 2012 | ISLPED | TSV array utilization in low-power 3D clock network design. | Xin Zhao, Sung Kyu Lim |
| 2012 | ITC | Scan test of die logic in 3D ICs using TSV probing. | Brandon Noia, Shreepad Panth, Krishnendu Chakrabarty, Sung Kyu Lim |
| 2012 | VTS | Transition delay fault testing of 3D ICs with IR-drop study. | Shreepad Panth, Sung Kyu Lim |
| 2011 | ASPDAC | Robust Clock Tree Synthesis with timing yield optimization for 3D-ICs. | Jae-Seok Yang, Jiwoo Pak, Xin Zhao, Sung Kyu Lim, David Z. Pan |
| 2011 | DAC | TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC. | Moongon Jung, Joydeep Mitra, David Z. Pan, Sung Kyu Lim |
| 2011 | DAC | Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC. | Chang Liu, Taigon Song, Jonghyun Cho, Joohee Kim, Joungho Kim, Sung Kyu Lim |
| 2011 | DATE | A novel TSV topology for many-tier 3D power-delivery networks. | Michael B. Healy, Sung Kyu Lim |
| 2011 | ICCAD | Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC. | Moongon Jung, Xi Liu, Suresh K. Sitaraman, David Z. Pan, Sung Kyu Lim |
| 2011 | ICCAD | Electromigration modeling and full-chip reliability analysis for BEOL interconnect in TSV-based 3D ICs. | Mohit Pathak, Jiwoo Pak, David Z. Pan, Sung Kyu Lim |
| 2011 | ICCD | Designing 3D test wrappers for pre-bond and post-bond test of 3D embedded cores. | Dean L. Lewis, Shreepad Panth, Xin Zhao, Sung Kyu Lim, Hsien-Hsin S. Lee |
| 2011 | ISLPED | Variation-aware clock network design methodology for ultra-low voltage (ULV) circuits. | Xin Zhao, Jeremy R. Tolbert, Chang Liu, Saibal Mukhopadhyay, Sung Kyu Lim |
| 2011 | VTS | Scan chain and power delivery network synthesis for pre-bond test of 3D ICs. | Shreepad Panth, Sung Kyu Lim |
| 2010 | ASPDAC | Buffered clock tree sizing for skew minimization under power and thermal budgets. | Krit Athikulwongse, Xin Zhao, Sung Kyu Lim |
| 2010 | ASPDAC | Power and slew-aware clock network design for through-silicon-via (TSV) based 3D ICs. | Xin Zhao, Sung Kyu Lim |
| 2010 | DAC | TSV stress aware timing analysis with applications to 3D-IC layout optimization. | Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee, Sung Kyu Lim, David Z. Pan |
| 2010 | ICCAD | Stress-driven 3D-IC placement with TSV keep-out zone and regularity study. | Krit Athikulwongse, Ashutosh Chakraborty, Jae-Seok Yang, David Z. Pan, Sung Kyu Lim |
| 2010 | ICCAD | Design method and test structure to characterize and repair TSV defect induced signal degradation in 3D system. | Minki Cho, Chang Liu, Dae Hyun Kim, Sung Kyu Lim, Saibal Mukhopadhyay |
| 2010 | ICCAD | Through-silicon-via management during 3D physical design: When to add and how many? | Mohit Pathak, Young-Joon Lee, Thomas Moon, Sung Kyu Lim |
| 2009 | ASPDAC | Thermal optimization in multi-granularity multi-core floorplanning. | Michael B. Healy, Hsien-Hsin S. Lee, Gabriel H. Loh, Sung Kyu Lim |
| 2009 | DATE | Co-design of signal, power, and thermal distribution networks for 3D ICs. | Young-Joon Lee, Yoon Jo Kim, Gang Huang, Muhannad S. Bakir, Yogendra K. Joshi, Andrei G. Fedorov, Sung Kyu Lim |
| 2009 | DATE | Decoupling capacitor planning with analytical delay model on RLC power grid. | Ye Tao, Sung Kyu Lim |
| 2009 | ICCAD | A study of Through-Silicon-Via impact on the 3D stacked IC layout. | Dae Hyun Kim, Krit Athikulwongse, Sung Kyu Lim |
| 2009 | ICCAD | Multi-functional interconnect co-optimization for fast and reliable 3D stacked ICs. | Young-Joon Lee, Rohan Goel, Sung Kyu Lim |
| 2009 | ICCAD | Pre-bond testable low-power clock tree design for 3D stacked ICs. | Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung Kyu Lim |
| 2009 | ISLPED | Slew-aware clock tree design for reliable subthreshold circuits. | Jeremy R. Tolbert, Xin Zhao, Sung Kyu Lim, Saibal Mukhopadhyay |
| 2008 | ASPDAC | A unified methodology for power supply noise reduction in modern microarchitecture design. | Michael B. Healy, Fayez Mohamood, Hsien-Hsin S. Lee, Sung Kyu Lim |
| 2008 | ASPDAC | Bus-aware microarchitectural floorplanning. | Dae Hyun Kim, Sung Kyu Lim |
| 2008 | ASPDAC | Buffered clock tree synthesis for 3D ICs under thermal variations. | Jacob R. Minz, Xin Zhao, Sung Kyu Lim |
| 2008 | ICCD | Global bus route optimization with application to microarchitectural design exploration. | Dae Hyun Kim, Sung Kyu Lim |
| 2007 | ASPDAC | An Efficient Computation of Statistically Critical Sequential Paths Under Retiming. | Mongkol Ekpanyapong, Xin Zhao, Sung Kyu Lim |
| 2007 | ASPDAC | Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling. | Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee |
| 2007 | FCCM | Rapid Prototyping of Large-scale Analog Circuits With Field Programmable Analog Array. | I. Faik Baskaya, Brian Gestner, Christopher M. Twigg, Sung Kyu Lim, David V. Anderson, Paul E. Hasler |
| 2007 | ICCAD | Thermal-aware Steiner routing for 3D stacked ICs. | Mohit Pathak, Sung Kyu Lim |
| 2007 | ICCD | Placement and routing of RF embedded passive designs in LCP substrate. | Mohit Pathak, Souvik Mukherjee, Madhavan Swaminathan, Ege Engin, Sung Kyu Lim |
| 2007 | ICCD | Whitespace redistribution for thermal via insertion in 3D stacked ICs. | Eric Wong, Sung Kyu Lim |
| 2006 | ASPDAC | Statistical Bellman-Ford algorithm with an application to retiming. | Mongkol Ekpanyapong, Thaisiri Watewai, Sung Kyu Lim |
| 2006 | DATE | Microarchitectural floorplanning under performance and thermal tradeoff. | Michael B. Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, Gabriel H. Loh |
| 2006 | DATE | Optical routing for 3D system-on-package. | Jacob R. Minz, Somaskanda Thyagaraja, Sung Kyu Lim |
| 2006 | DATE | 3D floorplanning with thermal vias. | Eric Wong, Sung Kyu Lim |
| 2006 | ICCAD | Decoupling capacitor planning and sizing for noise and leakage reduction. | Eric Wong, Jacob R. Minz, Sung Kyu Lim |
| 2006 | MICRO | A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design. | Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee |
| 2005 | ASPDAC | Wire congestion and thermal aware 3D global placement. | Karthik Balakrishnan, Vidit Nanda, Siddharth Easwar, Sung Kyu Lim |
| 2005 | ASPDAC | Placement for configurable dataflow architecture. | Mongkol Ekpanyapong, Michael B. Healy, Sung Kyu Lim |
| 2005 | ASPDAC | Partitioning and placement for buildable QCA circuits. | Ramprasad Ravichandran, Michael T. Niemier, Sung Kyu Lim |
| 2005 | FPL | Hierarchical Placement for Large-scale FPAA. | I. Faik Baskaya, Sasank Reddy, Sung Kyu Lim, David V. Anderson |
| 2005 | FPL | MILP-based Placement and Routing for Dataflow Architecture. | Michael B. Healy, Mongkol Ekpanyapong, Sung Kyu Lim |
| 2005 | ISCAS | Wire-driven microarchitectural design space exploration. | Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee |
| 2004 | ASPDAC | Performance-driven global placement via adaptive network characterization. | Mongkol Ekpanyapong, Sung Kyu Lim |
| 2004 | ASPDAC | Layer assignment for reliable system-on-package. | Jacob R. Minz, Sung Kyu Lim |
| 2004 | DAC | Profile-guided microarchitectural floorplanning for deep submicron processor design. | Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watewai, Hsien-Hsin S. Lee, Sung Kyu Lim |
| 2004 | DATE | Net and Pin Distribution for 3D Package Global Routing. | Jacob R. Minz, Mohit Pathak, Sung Kyu Lim |
| 2004 | ISCAS | Simultaneous delay and power optimization in global placement. | Mongkol Ekpanyapong, Karthik Balakrishnan, Vidit Nanda, Sung Kyu Lim |
| 2004 | ISCAS | Multi-layer floorplanning for reliable system-on-package. | Pun Hang Shiu, Ramprasad Ravichandran, Siddharth Easwar, Sung Kyu Lim |
| 2003 | ICCAD | A Novel Geometric Algorithm for Fast Wire-Optimized Floorplanning. | Peter G. Sassone, Sung Kyu Lim |
| 2000 | ASPDAC | Edge separability based circuit clustering with application to circuit partitioning. | Jason Cong, Sung Kyu Lim |
| 2000 | ASPDAC | Performance driven multiway partitioning. | Jason Cong, Sung Kyu Lim |
| 2000 | ASPDAC | Multi-way partitioning using bi-partition heuristics. | Maogang Wang, Sung Kyu Lim, Jason Cong, Majid Sarrafzadeh |
| 2000 | DAC | Performance driven multi-level and multiway partitioning with retiming. | Jason Cong, Sung Kyu Lim, Chang Wu |
| 2000 | ICCAD | Physical Planning with Retiming. | Jason Cong, Sung Kyu Lim |
| 1998 | ICCAD | Multiway partitioning with pairwise movement. | Jason Cong, Sung Kyu Lim |
| 1997 | ICCAD | Large scale circuit partitioning with loose/stable net removal and signal flow based clustering. | Jason Cong, Honching Peter Li, Sung Kyu Lim, Toshiyuki Shibuya, Dongmin Xu |