| 2019 | IOLTS | A Test Generation Method Based on k-Cycle Testing for Finite State Machines. | Yuya Kinoshita, Toshinori Hosokawa, Hideo Fujiwara |
| 2016 | ETS | A scheduling method for hierarchical testability based on test environment generation results. | Jun Nishimaki, Toshinori Hosokawa, Hideo Fujiwara |
| 2016 | ITC | A unified test and fault-tolerant multicast solution for network-on-chip designs. | Dong Xiang, Krishnendu Chakrabarty, Hideo Fujiwara |
| 2011 | ASPDAC | Secure scan design using shift register equivalents against differential behavior attack. | Hideo Fujiwara, Katsuya Fujiwara, Hideo Tamamoto |
| 2011 | ETS | F-Scan Test Generation Model for Delay Fault Testing at RTL Using Standard Full Scan ATPG. | Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara |
| 2011 | ETS | Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits. | Jaan Raik, Anna Rannaste, Maksim Jenihhin, Taavi Viilukas, Raimund Ubar, Hideo Fujiwara |
| 2011 | ETS | Temperature-Variation-Aware Test Pattern Optimization. | Tomokazu Yoneda, Makoto Nakao, Michiko Inoue, Yasuo Sato, Hideo Fujiwara |
| 2011 | ITC | Faster-than-at-speed test for increased test quality and in-field reliability. | Tomokazu Yoneda, Keigo Hori, Michiko Inoue, Hideo Fujiwara |
| 2010 | ASPDAC | Secure and testable scan design using extended de Bruijn graphs. | Hideo Fujiwara, Marie Engelene J. Obien |
| 2010 | DDECS | SREEP: Shift Register Equivalents Enumeration and Synthesis Program for secure scan design. | Katsuya Fujiwara, Hideo Fujiwara, Marie Engelene J. Obien, Hideo Tamamoto |
| 2010 | DDECS | A synthesis method to propagate false path information from RTL to gate level. | Satoshi Ohtake, Hiroshi Iwata, Hideo Fujiwara |
| 2010 | ETS | Test pattern selection to optimize delay test quality with a limited size of test set. | Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata, Hideo Fujiwara |
| 2010 | ETS | Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach. | Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara |
| 2010 | IOLTS | Aging test strategy and adaptive test scheduling for SoC failure prediction. | Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara |
| 2010 | ITC | Constrained ATPG for functional RTL circuits using F-Scan. | Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara |
| 2010 | ITC | RT-level design-for-testability and expansion of functional test sequences for enhanced defect coverage. | Alodeep Sanyal, Krishnendu Chakrabarty, Mahmut Yilmaz, Hideo Fujiwara |
| 2010 | VLSID | On Minimization of Test Application Time for RAS. | Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Hideo Fujiwara, Adit D. Singh |
| 2010 | VTS | Thermal-uniformity-aware X-filling to reduce temperature-induced delay variation for accurate at-speed testing. | Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Hideo Fujiwara |
| 2009 | ASPDAC | Fast false path identification based on functional unsensitizability using RTL information. | Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara |
| 2009 | ASPDAC | Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints. | Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara |
| 2009 | ETS | Partial Scan Approach for Secret Information Protection. | Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara |
| 2009 | VTS | A Synthesis Method to Alleviate Over-Testing of Delay Faults Based on RTL Don't Care Path Identification. | Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara |
| 2008 | ASPDAC | Localized random access scan: Towards low area and routing overhead. | Yu Hu, Xiang Fu, Xiaoxin Fan, Hideo Fujiwara |
| 2008 | DATE | Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects. | Tomokazu Yoneda, Hideo Fujiwara |
| 2007 | ASPDAC | Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses. | Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara |
| 2007 | ASPDAC | Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores. | Dan Zhao, Unni Chandran, Hideo Fujiwara |
| 2007 | DAC | A DFT Method for Time Expansion Model at Register Transfer Level. | Hiroyuki Iwata, Tomokazu Yoneda, Hideo Fujiwara |
| 2007 | DATE | Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers. | Tomokazu Yoneda, Masahiro Imanishi, Hideo Fujiwara |
| 2007 | ETS | Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints. | Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara |
| 2007 | ICCAD | Efficient path delay test generation based on stuck-at test generation using checker circuitry. | Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara |
| 2007 | ISCAS | Power-Aware Multi-Frequency Heterogeneous SoC Test Framework Design with Floor-Ceiling Packing. | Dan Zhao, Ronghua Huang, Tomokazu Yoneda, Hideo Fujiwara |
| 2007 | ITC | Fast and effective fault simulation for path delay faults based on selected testable paths. | Dong Xiang, Yang Zhao, Kaiwei Li, Hideo Fujiwara |
| 2007 | VTS | TAM Design and Optimization for Transparency-Based SoC Test. | Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara |
| 2007 | VTS | Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints. | Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara |
| 2006 | ASPDAC | A memory grouping method for sharing memory BIST logic. | Masahide Miyazaki, Tomokazu Yoneda, Hideo Fujiwara |
| 2006 | DATE | Functional constraints vs. test compression in scan-based delay testing. | Ilia Polian, Hideo Fujiwara |
| 2006 | DATE | Power-constrained test scheduling for multi-clock domain SoCs. | Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara |
| 2006 | ICCD | Power-Constrained SOC Test Schedules through Utilization of Functional Buses. | Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara |
| 2006 | ICCD | A New Class of Sequential Circuits with Acyclic Test Generation Complexity. | Chia Yee Ooi, Hideo Fujiwara |
| 2006 | ICCD | Generating Compact Robust and Non-Robust Tests for Complete Coverage of Path Delay Faults Based on Stuck-at Tests. | Dong Xiang, Kaiwei Li, Hideo Fujiwara, Jiaguang Sun |
| 2006 | VTS | BIST Pretest of ICs: Risks and Benefits. | Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara |
| 2005 | ETS | Acceleration of transition test generation for acyclic sequential circuits utilizing constrained combinational stuck-at test generation. | Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara |
| 2005 | FPL | Testing Superscalar Processors in Functional Mode. | Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara |
| 2005 | ISCAS | Instruction-based delay fault self-testing of pipelined processor cores. | Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara |
| 2005 | ITC | Design and analysis of multiple weight linear compactors of responses containing unknown values. | Thomas Clouqueur, Kamran Zarrineh, Kewal K. Saluja, Hideo Fujiwara |
| 2004 | ETS | An efficient scan tree design for test time reduction. | Yannick Bonhomme, Tomokazu Yoneda, Hideo Fujiwara, Patrick Girard |
| 2004 | ETS | A design methodology to realize delay testable controllers using state transition information. | Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara |
| 2004 | VLSID | Instruction-Based Delay Fault Self-Testing of Processor Cores. | Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara |
| 2003 | DATE | A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation Algorithms. | Satoshi Ohtake, Kouhei Ohtani, Hideo Fujiwara |
| 2003 | ITC | Area and Time Co-Optimization for System-on-a-Chip based on Consecutive Testability. | Tomokazu Yoneda, Tetsuo Uchiyama, Hideo Fujiwara |
| 2003 | VTS | Test Resource Partitioning and Optimization for SOC Designs. | Erik Larsson, Hideo Fujiwara |
| 2003 | VTS | Design for Consecutive Transparency of Cores in System-on-a-Chip. | Tomokazu Yoneda, Hideo Fujiwara |
| 2002 | ETS | Power constrained preemptive TAM scheduling. | Erik Larsson, Hideo Fujiwara |
| 2002 | ICCD | An Extended Class of Sequential Circuits with Combinational Test Generation Complexity. | Michiko Inoue, Chikateru Jinno, Hideo Fujiwara |
| 2002 | VTS | A Method of Test Generation for Path Delay Faults in Balanced Sequential Circuits. | Satoshi Ohtake, Hideo Fujiwara, Shunjiro Miwa |
| 2001 | ASPDAC | A DFT method for RTL circuits to achieve complete fault efficiency based on fixed-control testability. | Satoshi Ohtake, Shintaro Nagai, Hiroki Wada, Hideo Fujiwara |
| 2001 | DAC | A Framework for Low Complexity Static Learning. | Emil Gizdarski, Hideo Fujiwara |
| 2001 | VLSID | Testable Design of Sequential Circuits with Improved Fault Efficiency. | Debesh Kumar Das, Bhargab B. Bhattacharya, Satoshi Ohtake, Hideo Fujiwara |
| 2001 | VTS | SPIRIT: A Highly Robust Combinational Test Generation Algorithm. | Emil Gizdarski, Hideo Fujiwara |
| 2000 | ASPDAC | A non-scan DFT method at register-transfer level to achieve complete fault efficiency. | Satoshi Ohtake, Hiroki Wada, Toshimitsu Masuzawa, Hideo Fujiwara |
| 2000 | ICCAD | Test Generation for Acyclic Sequential Circuits with Hold Registers. | Tomoo Inoue, Debesh Kumar Das, Chiiho Sano, Takahiro Mihara, Hideo Fujiwara |
| 2000 | ITC | Non-scan design for testability for synchronous sequential circuits based on conflict analysis. | Dong Xiang, Yi Xu, Hideo Fujiwara |
| 2000 | VLSID | A New Definition and a New Class of Sequential Circuits with Combinational Test Generation Complexity. | Hideo Fujiwara |
| 2000 | VLSID | Design for Strong Testability of RTL Data Paths to Provide Complete Fault Efficiency. | Hiroki Wada, Toshimitsu Masuzawa, Kewal K. Saluja, Hideo Fujiwara |
| 1998 | ASPDAC | Partial Scan Design Methods Based on Internally Balanced Structure. | Tomoya Takasaki, Tomoo Inoue, Hideo Fujiwara |
| 1998 | GD | A Layout Adjustment Problem for Disjoint Rectangles Preserving Orthogonal Order. | Kunihiko Hayashi, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara |
| 1998 | OPODIS | SelfStabilizing WaitFree Clock Synchronization with Bounded Space. | Sen Moriya, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara |
| 1997 | ASPDAC | Non-scan design for testable data paths using thru operation. | Katsuyuki Takabatake, Toshimitsu Masuzawa, Michiko Inoue, Hideo Fujiwara |
| 1996 | ICDCS | A Snapshot Algorithm for Distributed Mobile Systems. | Yasuo Sato, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara |
| 1995 | VTS | A scheduling problem in test generation. | Tomoo Inoue, Hironori Maeda, Hideo Fujiwara |
| 1992 | ITC | Parity-Scan Design to Reduce the Cost of Test Application. | Hideo Fujiwara, Akihiro Yamamoto |
| 1989 | ICCAD | Optimal granularity of test generation in a distributed system. | Hideo Fujiwara, Tomoo Inoue |
| 1988 | ITC | Enhancing Random-Pattern Coverage of Programmable Logic Arrays via Masking Technique. | Hideo Fujiwara, Osamu Fujisawa, Kazunori Hikone |
| 1985 | ITC | A Testable Design of Programmable Logic Arrays with Universal Control and Minimal Overhead. | Hideo Fujiwara, Kewal K. Saluja, Kozo Kinoshita |
| 1983 | DAC | Test generation for scan design circuits with tri-state modules and bidirectional terminals. | Takuji Ogihara, Shinichi Murai, Yuzo Takamatsu, Kozo Kinoshita, Hideo Fujiwara |
| 1978 | DAC | LORES - Logic Reorganization System. | Shunichiro Nakamura, Shinichi Murai, Chiyoji Tanaka, Masayuki Terai, Hideo Fujiwara, Kozo Kinoshita |